Home | Legals | Sitemap | KIT

Performance Optimization for Multicore Chips

Performance Optimization for Multicore Chips
type: Seminar (S) links:
semester: WS 16/17
lecturer:

Heba Khdr
Santiago Pagani
Prof.Dr.Ing. Jörg Henkel

SWS: 2
ECTS: 3
lv-no.: 24371
information:

Course of Studies: Informatik Diplom/Master; Informationswirtschaft Diplom/Master.

The trend of increasing the number of integrated cores on a single chip has become apparent in chip manufacture. Some commercial industrial examples are 48-core Intel’s SCC, 61-core Intel Xeon Phi, and Tilera’s processor family. Along with the emerging of multicores, multi-threaded applications have emerged to run multiple threads of each application in parallel on the available cores. In order to optimize for performance in multicore chips, resource management is required to distribute the chip resources among the applications according to their parallelism levels and requirements. To be efficient, resource management needs to consider the implications of its decisions on the physical properties of the cores like temperature and power.

Language: English.

Application: Registration form.

Meeting Schedule: Will be informed vie email after registration.