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Low Power Design

Low Power Design
type: Vorlesung (V) links:
semester: SS 2017
place:

Raum -101, Geb. 50.34  INFORMATIK,
Kollegiengebäude am Fasanengarten

time:

ab 2017-04-27
am Do.
09:45 - 11:15 wöchentlich


2017-05-04
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-05-11
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-05-18
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-06-01
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-06-08
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-06-22
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-06-29
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-07-06
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-07-13
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-07-20
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2017-07-27
09:45 - 11:15 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

lecturer:

Anuj Pathania
Prof.Dr.Ing. Jörg Henkel

SWS: 2
ECTS: 3
lv-no.: 2424672
information:

Course of Studies: Informatik Bachelor/Master, Informationswirtschaft Bachelor

Smart embedded devices driven by advances in fields as diverse as automotive smart home, to high-tech like lithography or battery technology for IoT devices are now omnipresent in our lives. Today’s consumers have very high expectations from the embedded devices they own. Many emerging technologies such as virtual reality, robotics and artificial intelligence are limited in scope only by the performance of the underlying embedded devices. Unfortunately, performance of embedded devices is inherently constrained both by their limited cost, size as well as heat dissipating capacity and their limited on-board battery. The fact that all contemporary smartphones have multi-core chips running at low frequencies instead of single-core chips running at high frequencies can be attributed directly to the power consumption constraints imposed on them.

The constraints mandate highly optimized hardware-software co-design techniques for embedded devices that allows extraction of maximum performance with minimal power consumption. A good low power design requires all three building blocks of an embedded device – hardware, software and operating system – to work together synergistically. The lectures cover all the three aspects alongside their interactions from a low power design perspective in depth.

The lecture provides an overview of design methods, synthesis tools, estimation models, software techniques, operating system strategies, scheduling algorithms, etc., with the aim of minimizing the power consumption of embedded devices without compromising their performance. Both the research-relevant and industry-prevalent topics at different level of abstractions (from circuit to system) are discussed in this lecture.

Information

Language: English.

Recommendations: Module “Entwurf und Architekturen für eingebettete Systeme”. Basic knowledge from the module “Optimierung und Synthese Eingebetteter Systeme” is helpful but not essential for understanding of this lecture. The lecture is equally suitable for students from both computer science as well as electrical engineering department.

Teaching Objectives: Students are made aware of various low power design optimizations employed in state-of-the-art embedded devices. At the end of the lecture, the students will be able to recognize the challenges involved in crafting efficient low power designs and how to tackle them.

Downloads (nur für Studenten der Vorlesung).