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Performance Optimization for Multicore Chips

Performance Optimization for Multicore Chips
type: Seminar (S) links:
semester: WS 19/20
lecturer: Heba Khdr
Prof. Dr.-Ing. Jörg Henkel
SWS: 2
lv-no.: 2424371

The trend of increasing the number of integrated cores on a single chip has become apparent in chip manufacture. Some commercial industrial examples are 48-core Intel’s SCC, 61-core Intel Xeon Phi, and Tilera’s processor family. Along with the emerging of multicores, multi-threaded applications have emerged to run multiple threads of each application in parallel on the available cores. In order to optimize for performance in multicore chips, resource management is required to distribute the chip resources among the applications according to their parallelism levels and requirements. To be efficient, resource management needs to consider the implications of its decisions on the physical properties of the cores like temperature and power.

Content of teaching

We will focus on evaluating the state-of-the-art techniques of performance op-timization, like Linux Scheduler and Intel Turbo Boost. Furthermore, we will ana-lyze the influence of such techniques on the temperature and the power con-sumptions of the cores.