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Performance Optimization for Multicore Chips

Performance Optimization for Multicore Chips
type: Proseminar / Seminar (PS/S) links:
semester: SS 2020
lecturer: Dr.-Ing. Heba Khdr
Prof. Dr.-Ing. Jörg Henkel
SWS: 2
ECTS: 3
lv-no.: 2424136

The summer semester 2020 at KIT will start with online teaching. Please check the ILIAS courses for more details.

Notes

The trend of increasing the number of integrated cores on a single chip has become apparent in chip manufacture. Some commercial industrial examples are 48-core Intel’s SCC, 61-core Intel Xeon Phi, and Tilera’s processor family. Along with the emerging of multicores, multi-threaded applications have emerged to run multiple threads of each application in parallel on the available cores. In order to optimize for performance in multicore chips, a resource man-agement technique is required to distribute the chip’s resources among the ap-plications; i.e., determine the number of cores that should be allocated to each application and the voltage and frequency levels of these cores. Moreover, to be efficient, a resource management technique needs to consider the implica-tions of its decisions on the physical properties of the cores like the tempera-ture and the power consumption.

We will focus on evaluating the state-of-the-art techniques of performance optimization, like Linux Scheduler and Intel Turbo Boost. Furthermore, we will analyze the influence of such techniques on the temperature and the power consumptions of the cores.