The summer semester 2020 at KIT will start with online teaching. Please check the ILIAS courses for more details.
During this seminar, we will explore state-of-the-art for the power-efficient relia-bility and study different research solutions to improve soft-error resiliency in power efficient manner.
Among the other reliability threats due to physical limits of CMOS technology, radiation induced soft-errors or transient faults are also the most challenging threat to be handled.
With technology scaling the total soft error rate for a chip is seems to increase due to shrinking transistor dimensions and lower voltages that lead to smaller critical charges. These soft-errors occur in the physical layer and propagate to the upper software level as some undesired output. There is plethora of reliabil-ity optimization techniques at different system layers which are proposed in the literature, but power efficient reliability is required in the systems like many-core chip in which the maximum number of cores that can be simultaneously pow-ered-on is constrained by the Thermal Design Power (TDP). Therefore there is a great potential to involve different trade-off to improve system reliability but within such power constraint. For example there might be power-reliability trade-off in which reliability features can be controlled based on online estima-tion of power and vulnerability of the system.