This Lab is composed of two main experimentations. The first part consists of an exploration and analysis of the effect of loop transformation techniques and compiler optimizations in the power consumption, execution time and cache performance. SimpleScalar and Wattch simulators are used to run the applications and to obtain metrics to analyze.
Nowadays, power consumption is on of the most important criterion in the design of on-chip applications. Other design constraints, such as performance, were dominant in the past, but now it is imperative to optimize the power consumption, due it is a limiting factor. In fact, the power consumption has brought out many changes in the last decade: the fact that today we have multi-core chips instead of single core chips, is a direct result of the increase of power consumption. The power consumption is not only a matter of hardware, but also the software and the operating system decisively determine it. Therefore, this internship is indispensable for all who deal with on-chip systems at hardware and software level.
The second part of the lab consists of a Hardware/Software Co-design exploration using a High-Level Synthesis (HLS) Tool called “LegUp”. This tool is capable to take a C code implementation and to produce three types of implementations: a complete hardware (RTL) implementation, a software implementation to be executed in a MIPS soft-processor, and a hybrid implementation where one or more functions of a program are compiled to hardware accelerators with the remaining program segments running in software in a MIPS soft-processor. Considering these possibilities, the participants of the Lab will perform an exploration and analysis of the implementations in terms of required execution cycles, maximum frequency, area (FPGA resources), and power consumption. Altera Quartus tools are used to synthesize the implementations and obtain metrics, while Modelsim tool is used to perform simulations.