Among the other reliability threats due to physical limits of CMOS technology, radiation induced soft-errors or transient faults are also the most challenging threat to be handled. With technology scaling the total soft error rate for a chip is seems to increase due to shrinking transistor dimensions and lower voltages that lead to smaller critical charges. These soft-errors occur in the physical layer and propagate to the upper software level as some undesired output. There is plethora of reliability optimization techniques at different system layers which are proposed in the literature, but power efficient reliability is required in the systems like many-core chip in which the maximum number of cores that can be simultaneously powered-on is constrained by the Thermal Design Power (TDP). Therefore there is a great potential to involve different trade-off to improve system reliability but within such power constraint. For example there might be power-reliability trade-off in which reliability features can be controlled based on online estimation of power and vulnerability of the system.
During this semester, we will explore state-of-the-art for the power-efficient reliability and study different research solutions to improve soft-error resiliency in power efficient manner.
Application: Registration form
Meeting Schedule: Will be informed vie email after registration.