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Customized Embedded Processor Design for IoT

Customized Embedded Processor Design for IoT
type: Praktikum (P) links:
semester: WS 18/19
place:

Technologiefabrik
Room B2-308.1
(Bldg. 07.21, 2.OG)

time:

by agreement

lecturer: Sajjad Hussain
Dr.-Ing. Hussam Amrouch
Dr.-Ing. Lars Bauer
Prof. Dr.-Ing. Jörg Henkel
SWS: 4
ECTS: 4
lv-no.: 2424302
Description

Internet of Things (IoT) covers an ever-increasing range of ap plications. Smart sensors and embedded devices with networking capabilities connect to the Internet to provide advanced control and mon itoring services in healthcare, smart home, smart city and many other domains.

The design of embedded processors, especially for IoT, has experienced significant progress since past few years. This development has been characterized by the increasing demand for application-specif ic solutions for IoT in order to fulfil the diverse and contradictory requirements of low power consumption, high performance, low cost and most important ly an efficient time-to-market deployment of those processors.

Application Specific Instruction Set Processors (ASIP) are customized processors, having a specific instruction set targeting a specif ic application to achieve an optimal solution for the above requirements. This customization can be addressed at different architectural levels by defining customized instructions, including/excluding predefined hardware blocks or setting processor‘s parameters.

The focus of this lab is to get hands-on expertise of state-of-the-art ASIP Tool-Suite and practice optimized processor design for IoT. We will select an IoT application from healthcare domain (e.g. heart rate mo nitoring), profile them, design ASIP targeting power/area/speed eff iciency, and then use our infrastructure to benchmark the designed ASIP to com pare cost & benefit in terms of performance, power, area, etc.

The ASIP design flow includes analysing and profiling the targeted application, defining an ASIP accordingly, creating the speci al instruction, embedding required hardware blocks or configuring differ ent architectural parameters. The synthesizable hardware description and complet e compiler tool chain are generated automatically, and then t he customized processor is implement ed on an FPGA platform. This processor can be benchmarked for performance, area, and power constraints using ModelSim and Xilinx tools.

For this lab, the lab script and all exercises are available in English language.

Location and time: by agreement

Please register via campusmanagment

Content of teaching

The student will be supervised to learn how to adapt and customize a processor. This is done using state-of-the-art tool chains that can generate the required hardware description of the processor based on the optimization and customization that the student wants to do such as targeting performance and/or power goals. In addition, synthesis and implementation of the generated processor will be also done at the end using an FPGA platform.

Some pictures of the lab-overview (click to enlarge)