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Bauer

Dr.-Ing. Lars Bauer

Research Group Leader
room: B2-316.2
phone: +49 721 608-44218
fax: +49 721 608-43962
lars bauerArh5∂kit edu
http://ces.itec.kit.edu/~bauer
Haid-und-Neu-Str. 7
Bldg. 07.21
76131 Karlsruhe

Short Bio

Lars Bauer received his M.Sc. (Dipl.-Inform) and Ph.D. (Dr.-Ing.) in Computer Science from the University of Karlsruhe (TH) Germany in 2004 and 2009, respectively. He is currently a research assistant, lecturer, and group leader at the Chair for Embedded Systems (CES) at the Karlsruhe Institute of Technology (KIT). His main research interests are extensible processors and reconfigurable and adaptive computing systems with a special interest on dynamically varying run-time situations and concepts that allow systems to adapt to changing requirements. He received the EDAA Outstanding Dissertations Award, the FZI Outstanding Dissertation Award, the AHS'11 best paper award, and the DATE'08 best paper award for his work on adaptive reconfigurable processors. Lars Bauer is a principal investigator in the 'Invasive Computing' research initiative (DFG SFB TR-89) and he is the head of the KIT Young Investigator Group (YIG) "Methods and Architectures for emerging dynamically reconfigurable systems".

pdficon  Curriculum Vitae

 

Research Interests

 

Publications

Book

jh_book2

Lars Bauer, Jörg Henkel
Run-time Adaptation for Reconfigurable Embedded Processors
Springer Science+Business Media, LLC , 2011
ISBN 978-1-4419-7411-2
e-ISBN 978-1-4419-7412-9
DOI 10.1007/978-1-4419-7412-9

Journals / Transactions

  • Artjom Grudnitsky, Lars Bauer, Jörg Henkel
    Efficient Partial Online-Synthesis of Special Instructions for Reconfigurable Processors
    in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2016 (accepted).
     
  • Marvin Damschen, Lars Bauer, Jörg Henkel
    Timing Analysis of Tasks on Runtime Reconfigurable Processors
    in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2016 (accepted).
     
  • Fazal Hameed, Lars Bauer, Jörg Henkel:
    Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’16)
    April 2016
    Vol. 35, Issue 4, pp. 651-664, DOI
     
  • Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel:
    Multicast FullHD H.264 Intra Video Encoder Architecture
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’15)
    Dec. 2015
    Vol. 34, Issue 12, pp. 2049-2053, DOI
     
  • Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
    Resource-awareness on heterogeneous MPSoCs for image processing
    in Journal of Systems Architecture (JSA’15)
    November 2015
    Vol. 61, Issue 10, pp. 668-680, DOI
     
  • Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes M. Kühn,
    Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang:
    Adaptive multi-layer techniques for increased system dependability
    it – Information Technology (IT’15)
    June 2015
    Volume 57, Issue 3, pp. 149-158
    Invited Article for the Special Issue: Dependable Embedded Systems
    pdficon Paper (pdf ~0.8 MB)
     
  • Muhammad Shafique, Lars Bauer, Jörg Henkel:
    Adaptive Energy Management for Dynamically Reconfigurable Processors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’14)
    January 2014
    Volume 33, Issue 1, pp. 50-63
    pdficon Paper (pdf ~20.5 MB)
     
  • Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
    Test Strategies for Reliable Runtime Reconfigurable Architectures
    IEEE Transactions on Computers (TC’13)
    Special Section on Adaptive Hardware and Systems, August 2013
    Volume 62, Issue 8, pp. 1494-1507
    pdficon Paper (pdf ~2.8 MB)
     
  • Muhammad Shafique, Lars Bauer, Jörg Henkel:
    Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms
    Journal of Signal Processing Systems (JSPS’10)
    Special Issue: Embedded Multimedia Systems, August 2010
    Volume 60, Issue 2, pp. 183-210
    pdficon Paper (pdf ~1.8 MB)
     
  • Lars Bauer, Muhammad Shafique, Jörg Henkel:
    Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation
    IEEE Transaction on Very Large Scale Integration (TVLSI’08)
    Special Section on Application-Specific Processors, October 2008
    Volume 16, Issue 10, pp. 1295-1308
    pdficon Paper (pdf ~2.3 MB)

Conferences

ICCAD2015 Hongyan Zhang, Lars Bauer, Jörg Henkel:
Resource Budgeting for Reliability in Reconfigurable Architectures
ACM/EDAC/IEEE 53rd Design Automation Conference (DAC´16)
Austin, TX, USA, June 5-9, 2016 (accepted).
ICCAD2015 Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures
IEEE/ACM International Conference on Computer-Aided Design (ICCAD´15)
Austin, TX, USA, November 2-6, 2015
ESTIMedia15 Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare, Jörg Henkel:
Floating Point Acceleration for Stream Processing Applications in Dynamically Reconfigurable Processors
IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia´15)
Amsterdam, The Netherlands, October 8-9, 2015
Invited Paper for the Special Session "Dynamics and Predictability in Stream Processing -- A Contradiction?"
codesisss2015 Farzad Samie, Lars Bauer, Jörg Henkel:
An Approximate Compressor for Wearable Biomedical Healthcare Monitoring Systems
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS´15)
Amsterdam, The Netherlands, October 4-9, 2015
date15 Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel:
Online Binding of Applications to Multiple Clock Domains in Shared FPGA-based Systems
IEEE/ACM 18th Design, Automation and Test in Europe Conference (DATE´15)
Grenoble, France, March 2015
pp. 25-30
pdficon Paper (pdf ~0.2 MB)
date15 Sebastian Kobbe, Lars Bauer, Jörg Henkel:
Adaptive on-the-fly Application Performance Modeling for Many Cores
IEEE/ACM 18th Design, Automation and Test in Europe Conference (DATE´15)
Grenoble, France, March 2015
pp. 730-735
pdficon Paper (pdf ~0.3 MB)
CASES´14 Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
COREFAB: Concurrent Reconfigurable Fabric Utilization in Heterogeneous Multi-Core Systems
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES´14)
New Delhi, India, October 2014
pdficon Paper (pdf ~0.4 MB)
CASES´14 Martin Haaß, Lars Bauer, Jörg Henkel:
Automatic Custom Instruction Identification in Memory Streaming Algorithms
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES´14)
New Delhi, India, October 2014
pdficon Paper (pdf ~0.3 MB)
DAC´14 Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture
IEEE/ACM Design Automation Conference (DAC´14)
San Francisco, CA, USA, June 2014
pdficon Paper (pdf ~0.3 MB)
DAC´14 Hongyan Zhang, Michael Kochte, Michael Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems
IEEE/ACM Design Automation Conference (DAC´14)
San Francisco, CA, USA, June 2014
pdficon Paper (pdf ~0.6 MB)
DAC´14 Jörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique:
Multi-Layer Dependability: From Microarchitecture to Application Level
IEEE/ACM Design Automation Conference (DAC´14)
San Francisco, CA, USA, June 2014
(Invited Paper for the Special Session "Embedded Resiliency: Approaches for the Next Decade")
pdficon Paper (pdf ~2.2 MB)
FPGA´14 Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA´14)
Monterey, CA, USA, February 2014
pp. 127-136
pdficon Paper (pdf ~1.1 MB)
CASES´13 Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel:
Hardware Acceleration for Programs in SSA Form
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES´13)
Montreal, Canada, September/October 2013
pdficon Paper (pdf ~0.6 MB)
CASES´13 Fazal Hameed, Lars Bauer, Jörg Henkel:
Simultaneously Optimizing DRAM Cache Hit Latency and Miss Rate via Novel Set Mapping Policies
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES´13)
Montreal, Canada, September/October 2013
pdficon Paper (pdf ~0.8 MB)
CODES+ISSS´13 Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing Inter-Core Cache Contention with an Adaptive Bank Mapping Policy in DRAM Cache
IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS´13)
Montreal, Canada, September/October 2013
pdficon Paper (pdf ~0.8 MB)
ITC´13 Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel:
Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures
IEEE International Test Conference (ITC´13)
Anaheim, CA, USA, September 2013
pp. 1-10
pdficon Paper (pdf ~0.7 MB)
DAC´13 Jörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani Nassif, Muhammad Shafique, Mehdi Tahoori, Norbert Wehn:
Reliable On-Chip Systems in the Nano-Era: Lessons Learnt and Future Trends
IEEE/ACM Design Automation Conference (DAC´13)
Austin, TX, USA, June 2013
pdficon Paper (pdf ~0.8 MB)
DATE´13 Fazal Hameed, Lars Bauer, Jörg Henkel:
Adaptive Cache Management for a combined SRAM and DRAM Cache Hierarchy for Multi-Cores
IEEE/ACM 16th Design Automation and Test in Europe Conference (DATE´13)
Grenoble, France, March 2013
pp. 77-82
pdficon Paper (pdf ~0.5 MB)
DATE´13 Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel:
An H.264 Quad-FullHD Low-Latency Intra Video Encoder
IEEE/ACM 16th Design Automation and Test in Europe Conference (DATE´13)
Grenoble, France, March 2013
pp. 115-120
pdficon Paper (pdf ~0.5 MB)
IOLTS´12 Mohammed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Transparent Structural Online Test for Reconfigurable Systems
IEEE International On-Line Testing Symposium (IOLTS´12)
Sitges, Spain, June 2012
pp. 37-42
pdficon Paper (pdf ~0.6 MB)
AHS´12 Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel:
OTERA: Online Test Strategies for Reliable Reconfigurable Architectures
NASA/ESA Conference on Adaptive Hardware and Systems (AHS´12)
Nuremberg, Germany, June 2012
pp. 38-45
(Invited Paper for the Special Session "Dependability by Reconfigurable Hardware")
pdficon Paper (pdf ~0.9 MB)
FCCM´12 Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel:
PATS: a Performance Aware Task Scheduler for Runtime Reconfigurable Processors
20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM´12)
Toronto, Canada, April/May 2012
pp. 208-215
pdficon Paper (pdf ~0.3 MB)
DATE´12 Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures
IEEE/ACM 15th Design Automation and Test in Europe Conference (DATE´12)
Dresden, Germany, March 2012
pp. 1555-1560
pdficon Paper (pdf ~0.3 MB)
DATE´12 Fazal Hameed, Lars Bauer, Jörg Henkel:
Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation
IEEE/ACM 15th Design Automation and Test in Europe Conference (DATE´12)
Dresden, Germany, March 2012
pp. 485-490
pdficon Paper (pdf ~0.4 MB)
ASP-DAC´12 J. Henkel, A. Herkersdorf, L. Bauer, T. Wild, M. Hübner, R.K. Pujari, A. Grudnitsky, J. Heisswolf, A. Zaib, B. Vogel, V. Lari, S. Kobbe:
Invasive Manycore Architectures
17th Asia and South Pacific Design Automation Conference (ASP-DAC´12)
Sydney, Australia, January/February 2012
pp. 193-200
(Invited Paper for the Special Session "Design and Prototyping of Invasive MPSoC Architectures")
pdficon Paper (pdf ~0.8 MB)
CODES+ISSS´11 Sebastian Kobbe, Lars Bauer, Jörg Henkel, Daniel Lohmann, Wolfgang Schröder-Preikschat:
DistRM: Distributed Resource Management for On-Chip Many-Core Systems
IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS´11)
Taipei, Taiwan, October 2011
pp. 119-128
pdficon Paper (pdf ~0.9 MB)
CODES+ISSS´11 Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
Adaptive Resource Management for Simultaneous Multitasking in Mixed-Grained Reconfigurable Multi-core Processors
IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS´11)
Taipei, Taiwan, October 2011
pp. 365-374
pdficon Paper (pdf ~1.2 MB)
CODES+ISSS´11 J. Henkel, L. Bauer, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, J. Teich, N. Wehn, H.-J. Wunderlich:
Design and Architectures for Dependable Embedded Systems
IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS´11)
Taipei, Taiwan, October 2011
pp. 69-78
(Invited Paper for the Special Session "Design and Architectures for Dependable Embedded Systems")
pdficon Paper (pdf ~1.9 MB)
ERSA´11 Jörg Henkel, Lars Bauer, Michael Hübner, Artjom Grudnitsky:
i-Core: A run-time adaptive processor for embedded multi-core systems
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA´11)
Las Vegas, Nevada, USA, July 2011
(Invited Paper for the Special Session "Runtime Adaptive Embedded Systems and Architectures")
pdficon Paper (pdf ~0.4 MB)
AHS´11 Lars Bauer, Muhammad Shafique, Jörg Henkel:
Concepts, Architectures, and Run-time Systems for Efficient and Adaptive Reconfigurable Processors
NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS´11)
San Diego, CA, USA, June 2011
pp. 80-87
(Invited Paper for the Special Session "Dynamically Reconfigurable Embedded Systems")
pdficon Paper (pdf ~0.5 MB)
FCCM´11 Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Juergen Becker:
Run-Time Resource Allocation for Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors
IEEE 19th Symposium on Field-Programmable Custom Computing Machines (FCCM´11)
Salt Lake City, Utah, USA, May 2011
pp. 29-32
pdficon Paper (pdf ~0.4 MB)
DATE´11 Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions
IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE´11)
Grenoble, France, March 2011
pp. 1554-1559
pdficon Paper (pdf ~0.6 MB)
DATE´11 Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jörg Henkel:
Minority-Game-based Reconfigurable Fabric Resource Allocation for Run-Time Reconfigurable Multi-Core Processors
IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE´11)
Grenoble, France, March 2011
pp. 1261-1266
pdficon Paper (pdf ~0.5 MB)
ICCAD´10 Muhammad Shafique, Lars Bauer, Jörg Henkel:
Selective Instruction Set Muting for Energy-Aware Adaptive Processors
IEEE/ACM 28th International Conference on Computer-Aided Design (ICCAD´10)
San Jose, CA, USA, November 2010
pp. 353-360
pdficon Paper (pdf ~0.7 MB)
DATE´10 Ralf Koenig, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Juergen Becker, Jörg Henkel:
KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture
IEEE/ACM 13th Design Automation and Test in Europe Conference (DATE´10)
Dresden, Germany, March 2010
pp. 819-824
pdficon Paper (pdf ~0.9 MB)
DATE´10 Muhammad Shafique, Lars Bauer, Jörg Henkel:
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting Scheme for Energy-Aware Motion Estimation in H.264/MPEG-4 AVC Video Encoder
IEEE/ACM 13th Design Automation and Test in Europe Conference (DATE´10)
Dresden, Germany, March 2010
pp. 1725-1730
pdficon Paper (pdf ~0.7 MB)
ICCAD´09 Muhammad Shafique, Lars Bauer, Jörg Henkel:
REMiS: Run-time Energy Minimization Scheme in a Reconfigurable Processor with Dynamic Power-Gated Instruction Set
IEEE/ACM 27th International Conference on Computer-Aided Design (ICCAD´09)
San Jose, California, USA, November 2009
pp. 55-62
pdficon Paper (pdf ~0.5 MB)
CODES+ISSS´09 Lars Bauer, Muhammad Shafique, Jörg Henkel:
MinDeg: A Performance-guided Replacement Policy for Run-time Reconfigurable Accelerators
IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS´09)
Grenoble, France, October 2009
pp. 335-342
pdficon Paper (pdf ~1.5 MB)
DATE´09 Lars Bauer, Muhammad Shafique, Jörg Henkel:
Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors
IEEE/ACM 12th Design Automation and Test in Europe Conference (DATE´09)
Nice, France, April 2009
pp. 958-963
pdficon Paper (pdf ~0.8 MB)
DATE´09 Muhammad Shafique, Lars Bauer, Jörg Henkel:
A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec
IEEE/ACM 12th Design Automation and Test in Europe Conference (DATE´09)
Nice, France, April 2009
pp. 1434-1439
pdficon Paper (pdf ~0.6 MB)
FPL´08 Lars Bauer, Muhammad Shafique, Jörg Henkel:
A Computation- and Communication-Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor
IEEE 18th International Conference on Field Programmable Logic and Applications (FPL´08)
Heidelberg, Germany, September 2008
pp. 203-208
pdficon Paper (pdf ~0.5 MB)
ISLPED´08 Muhammad Shafique, Lars Bauer, Jörg Henkel:
3-Tier Dynamically Adaptive Power-Aware Motion Estimator for H.264/AVC Video Encoding
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED´08)
Bangalore, India, August 2008
pp. 147-152
pdficon Paper (pdf ~3.7 MB)
DAC´08 Lars Bauer, Muhammad Shafique, Jörg Henkel:
Run-time Instruction Set Selection in a Transmutable Embedded Processor
ACM/IEEE/EDA 45th Design Automation Conference (DAC´08)
Anaheim, CA, USA, June 2008
pp. 56-61
pdficon Paper (pdf ~1.0 MB)
DATE´08 Lars Bauer, Muhammad Shafique, Stephanie Kreutz, Jörg Henkel:
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
IEEE/ACM 11th Design Automation and Test in Europe Conference (DATE´08)
Munich, Germany, March 2008
pp. 752-757
pdficon Paper (pdf ~1.4 MB)
SASO´07 Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel:
A Self-Adaptive Extensible Embedded Processor
IEEE/ACM First International Conference on Self-Adaptive and Self-Organizing Systems (SASO´07)
Boston, MA, USA, July 2007
pp. 344-347
pdficon Paper (pdf ~0.4 MB)
pdficon Slides (pdf ~0.9 MB)
DAC´07 Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel:
RISPP: Rotating Instruction Set Processing Platform
ACM/IEEE/EDA 44th Design Automation Conference (DAC´07)
San Diego, CA, USA, June 2007
pp. 791-796
pdficon Paper (pdf ~0.6 MB)
Slides (ppt ~4.5 MB)

Workshops

Jörg Henkel, Lars Bauer, Artjom Grudnitsky, Hongyan Zhang:
Adaptive Embedded Computing with i-Core
ACM SIGBED Review – Special Issue on the 6th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES), Volume 11, pp. 20–21
Extended Abstract for Keynote Talk
Berlin, Germany, October 2014
pdficon Paper (pdf ~0.1 MB)
EuroSys´11 Benjamin Oechslein, Jens Schedel, Jürgen Kleinöder, Lars Bauer, Jörg Henkel, Daniel Lohmann, Wolfgang Schröder-Preikschat:
OctoPOS: A Parallel Operating System for Invasive Computing
Systems for Future Multi-Core Architectures (SFMA´11)
Salzburg, Austria, April 2011
pdficon Paper (pdf ~0.9 MB)
Embedded System Week´07 Lars Bauer, Muhammad Shafique, Jörg Henkel:
Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation
5th Workshop on Application Specific Processors (WAS´P07)
Salzburg, Austria, October 2007
pp. 39-46
pdficon Paper (pdf ~0.5 MB)
Embedded System Week´07 Muhammad Shafique, Lars Bauer, Jörg Henkel:
Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms
5th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia´07)
Salzburg, Austria, October 2007
pp. 119-124
pdficon Paper (pdf ~0.2 MB)

Ph.D. Forums

DATE'14 Fazal Hameed, Lars Bauer, Jörg Henkel:
On-Chip DRAM Last Level Cache Policies for Multi-Core Systems
IEEE/ACM 17th Design Automation and Test in Europe Conference (DATE'14)
Dresden, Germany, March 2014
pdficon Poster (pdf ~0.1MB)  
DATE'11 Muhammad Shafique, Lars Bauer, Jörg Henkel:
Architectures for Adaptive Low-Power Embedded Multimedia Systems
IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE'11)  
Grenoble, France, March 2011
pdficon Poster (pdf ~1.4MB)  
FPL'09 Lars Bauer, Muhammad Shafique, Jörg Henkel:
RISPP: A Run-time Adaptive Reconfigurable Embedded Processor
IEEE 19th International Conference on Field Programmable Logic and Application (FPL'09)
Prague, Czech Republic, August/September 2009
pp. 725-726
pdficon Paper (pdf ~0.8 MB)  
DAC'09 Lars Bauer, Muhammad Shafique, Jörg Henkel:
RISPP: A Run-time Adaptive Reconfigurable Embedded Processor
12th ACM/SIGDA Ph.D. Forum at DAC 
ACM/IEEE/EDA 46th Design Automation Conference (DAC'09)
San Francisco, CA, USA, July 2009
pdficon Poster (pdf ~3.4 MB)  

Invited Talks

Adaptive multi-layer techniques for increased system dependability
8th GMM/ITG/GI Zuverlässigkeit und Entwurf (ZuE) Fachtagung (Reliability by Design Conference), Special Session on "Dependable Embedded Systems"
Siegen, Germany, September 2015
Design and Management of Heterogeneous Adaptive Multi-core Processor Architectures
System- and Computer-Architecture Colloquium
Hannover, Germany, September 2015
Reliable Runtime Reconfigurable Architectures
2nd GI/ITG Workshop on Reconfigurable Systems: Architectures, Tools, Applications
Darmstadt, Germany, June 2015
The 'Invasive Computing' Paradigm
University of Southampton, UK, February 2014
Design and Management of heterogeneous Multi-/Many-core SoCs
TUB System-on-chip colloquium
Berlin, Germany, December 2013
Adaptive Reconfigurable Instruction Set Processors
GI/ITG Workshop on Reconfigurable Systems: Architectures, Tools, Applications
Darmstadt, Germany, April 2011
pdficon Slides (pdf ~8.7 MB)
Intel Workshop Automatic extraction and selection of complex modular Special Instructions for reconfigurable processor architectures
Intel Workshop on "Approaches and tools for efficient design of SoCs"
St. Petersburg, Russia, November 2010
Dagstuhl Run-time Adaptation for Reconfigurable Embedded Processors
Dagstuhl Seminar on "Dynamically Reconfigurable Architectures
Schloss Dagstuhl - Leibniz Center for Informatics, Germany, July 2010
MPSoC'10 KAHRISMA: A Multi-grained Reconfigurable Multicore Architecture
10th International Forum on Embedded MPSoC and Multicore (MPSoC´10)
Gifu city, Gifu, Japan, June/July 2010
pdficon Slides (pdf ~1.4 MB)
SPP-RR 1148 RISPP: Rotating Instruction Set Processing Platform
Colloquium of the DFG Priority Program 1148 "Rekonfigurierbare Rechensysteme" (Reconfigurable Computing Systems) (SPP-RR)
Karlsruhe, Germany, September 2009
pdficon Slides (pdf ~5.3 MB)  
MPSoC'09 Classifying and Evaluating Performance-relevant Parameters for Reconfigurable Processors
9th International Forum on Embedded MPSoC and Multicore (MPSoC´09)
Savannah, GA, USA, August 2009

Posters

  • Lars Bauer, Rainer Buchty, Thomas Ebi, David Kramer, Alexander von Renteln, Christian Schuck Prof. K. Brändle, Prof. J. Becker, Prof. U. Brinkschulte, Prof. J. Henkel, Prof. W. Karl:
    DodOrg: Stability and Robustness
    8th Organic Computing Colloquium 2009, Bochum, 19/20th February 2009
    pdficon pdf (~0.8 MB)
  • Lars Bauer, Rainer Buchty, Florian Kaiser, Alexander von Renteln, Christian Schuck, Michael Wenz Prof. K. Brändle, Prof. J. Becker, Prof. U. Brinkschulte, Prof. J. Henkel, Prof. W. Karl, Prof. H. Wörn:
    DodOrg Project Overview
    4th Organic Computing Colloquium 2007, Berlin, 15/16th February 2007
    pdficon pdf (~1.1 MB)
  • Simulation Framework: Florian Kaiser, Daniel Heyder, Michael Pressler, Prof. Dr. J. Henkel Hardware Prototype: Lars Bauer, Christian Krämer, Tibor Kampeis, Artjom Grudnitsky, Talal Bonny, Prof. Dr. J. Henkel:
    DodOrg Case Study: Task mapping, scheduling and swapping-on-the-fly
    3rd Organic Computing Colloquium 2006, Stuttgart, 14/15th September 2006
    pdficon pdf (~0.4 MB)
  • M.A. Al Faruque, L. Bauer, T. Bonny, S. Gottfried, J. Henkel:
    Power and Performance for ASIPs
    Poster Presentation, Embedded Systems Day 2005, Karlsruhe, 14th March 2005
    pdficon pdf (~0.2 MB)
  • M.A. Al Faruque, L. Bauer, T. Bonny, S. Gottfried, J. Henkel:
    Embedded Systems Lab: Design Space Exploration for ASIPs
    Poster Presentation, Embedded Systems Day 2005, Karlsruhe, 14th March 2005
    pdficon pdf (~0.1 MB)

Misc

  • Lars Bauer (Supervisor: Jörg Henkel):
    RISPP: A Run-time Adaptive Reconfigurable Embedded Processor
    Ph.D. Thesis (Doktorarbeit), University of Karlsruhe, Germany, 15.12.2009
    pdficon pdf (~9.5 MB)
  • Lars Bauer (Supervisor: Jörg Henkel):
    Entwicklung einer Prototyping-Umgebung für anwendungsspezifische Eingebettete Prozessoren
    Diploma Thesis, University of Karlsruhe, Germany, 23.11.2004
    pdficon pdf (~1.2 MB)
  • Lars Bauer (Supervisor: Carsten Kübler, Heinz Wörn):
    Effiziente Darstellung großer texturierter Modelle mit VTK
    Student Research Project, University of Karlsruhe, September 2003
    pdficon pdf (~0.8 MB)
  • Lars Bauer (Supervisor: Jürgen Reuter):
    Systeme für Hochleistungsrechnen - Disk Scheduling
    Seminar Paper, University of Karlsruhe, September 2003
    pdficon pdf (~0.2 MB)

 

Teaching

Supervision

Diploma / Master Thesis

Allgemeine Informationen:
Es gibt fast immer neue Diplomarbeiten, die wegen ihrer hohen Aktualität nicht in dieser Liste angekündigt werden oder für welche die Idee sogar erst im gemeinsamen Gespräch entsteht. Darum lohnt es sich in jedem Fall, persönlich bei mir vorbeizukommen, um auch die aktuellsten Aufgaben vorgestellt bekommen zu können. Die meisten Aufgaben werden dabei mehr oder weniger stark unser RISPP Projekt betreffen, das Tätigkeiten von Hardwareentwicklung über Konzeptsimulation bis hin zu Algorithmenentwicklung umfasst.

  • Thema: Kommunikationsstrukturen fuer i-Core
    Status: Running by Jörg Suter
  • Entwicklung und Integration eines Permutationsregisterfiles für den Leon3
    Status: Running by Tobias Modschiedler
  • Erweiterung eines LEON3 SoC um rekonfigurierbare anwendungsspezifische Beschleuniger
    Status: Running by Martin Riedlberger
  • Entwicklung von Kameraanbindungen und Vorverarbeitungsfiltern für FPGA-basierte Video-Kodierung
    Status: Completed by Marcus Eggenberger
  • Operating system strategies for multitasking of a dynamically reconfigurable processor
    Status: Completed by Matthias Rosenfelder
  • Designing and prototyping a partially reconfigurable processor framework with a HW/SW Co-Designed run-time system
    Status: Completed by Frank Birkle
  • Design and implementation of an extensible ASIP for an H.264 Video Encoder
    Status: Completed by Roman Sinawski
  • Extending the RISPP Simulator with Floorplan-Aware Special Instruction Management and Execution
    Status: Completed by Artjom Grudnitsky
  • Visualisierung ereignisbasierter interner Abläufe in rekonfigurierbaren Prozessoren
    Status: Completed by Patrick Koffler; Flyer: pdficon pdf
  • Extending an application specific processor towards dynamic partial reconfiguration
    Status: Completed by Hongzhang Chen
  • Simulation und Messung des Energieverbrauchs eines Rekonfigurierbaren Eingebetteten Prozessors
    Status: Completed by Weiwei Cheng
  • Design and Implementation of a Reconfigurable Processor with Adaptive Reconfiguration Management
    Status: Completed by Christian Krämer
  • Konzeption und Evaluierung einer Methodik zur Rekonfigurationsentscheidung eines dynamischen ASIPs
    Status: Completed by Stephanie Kreutz
  • Graphenanalyse zur Bestimmung von Vorhersagepunkten für Spezialbefehle
    Status: Completed by Simon Kramer
  • Implementierung eines Prototypen zur partiellen Laufzeitrekonfiguration
    Status: Completed by Francois Blassmann
  • Entwicklung eines Rekonfigurationsmanagers für einen Applikationsspezifischen Prozessor
    Status: Completed by Dirk Teufel; Flyer: pdficon pdf
  • Entwurf und Implementierung einer Grafikschnittstelle für ein FPGA Prototyping-System
    Status: Completed by Peter Vohmann; Flyer: pdficon pdf

Student Research Projects / Bachelor Theses

Allgemeine Informationen:
Es gibt fast immer neue Studienarbeiten, die wegen ihrer hohen Aktualität nicht in dieser Liste angekündigt werden oder für welche die Idee sogar erst im gemeinsamen Gespräch entsteht. Darum lohnt es sich in jedem Fall, persönlich bei mir vorbeizukommen, um auch die aktuellsten Aufgaben vorgestellt bekommen zu können. Die meisten Aufgaben werden dabei mehr oder weniger stark unser RISPP Projekt betreffen, das Tätigkeiten von Hardwareentwicklung üfür Konzeptsimulation bis hin zu Algorithmenentwicklung umfasst.

  • Thema: Anwendungsspezifische rekonfigurierbare Beschleuniger fuer i-Core Status: Running by Eduard Maier
    Extending a simulator for a reconfigurable processor with behavioral accuracy
    Status: Running by Marc Typke
  • Entwicklung einer grafischen Arbeitumsgebung zur Implementierung und Überprüfung von Spezialbefehlen
    Status: Completed by Michael Mutter
  • Konzeption und Implementierung von Multi-Tasking-Strategien für einen adaptiven, dynamisch rekonfigurierbaren Prozessor
    Status: Completed by Thomas Romberg
  • Entwicklung eines IP-Cores zur Erfassung und Vorverarbeitung von Videodaten auf einem FPGA
    Status: Completed by Jan Micha Borrmann
  • Untersuchung verschiedener Implementierungen von Spezialbefehlen für dynamisch rekonfigurierbare Prozessoren
    Status: Completed by Ekrem Karaman
  • Designing a customizable framework with exchangeable modules for partially reconfigurable hardware
    Status: Completed by Artjom Grudnitsky
  • A simulation environment for reconfigurable processor architectures
    Status: Completed by Roland Sedler
  • Entwicklung eines SRAM-PCBs für ein Xilinx FPGA-Board
    Status: Completed by Hongzhang Chen
  • Designing an Optimized Application Specific Instruction Set Processor
    Status: Completed von Wei Huang; Flyer: pdficon pdf
  • Implementierung eines Permutations-Registerfiles zur Beschleunigung des Kompilats von SSA-basierten Übersetzern
    Status: Completed by Julian Schill
  • Evaluierung von Debuggingwerkzeugen für Xilinx FPGAs
    Status: Completed by Christoph Brückner
    Pictures of the developed PCB for connecting the Logic Analyser: First Version, Connecting the FPGA Board
  • Messen des Leistungsverbrauches beim partiellen Rekonfigurieren eines FPGAs
    Status: Completed by Andreas Becker; Flyer: pdficon pdf
  • Lokales Scheduling für die verteilte Ausführung von Task-Graphen in einem heterogenen Multiprozessor System
    Status: Completed by Michael Pressler; Thesis: pdficon pdf
  • Mapping von Task-Graphen in einem heterogenen Multiprozessor System
    Status: Completed by Daniel Heyder; Thesis: pdficon pdf
  • Entwicklung eines Designs zur partiellen Selbstrekonfiguration mit PlanAhead
    Status: Completed von Florian Fetz; Thesis: pdficon pdf
  • Implementierung einer I2C Schnittstelle für ein FPGA Prototyping Board und Anbindung eines Touch Screen LCDs zur Steuerung von ASIPs
    Status: Completed von Christian Krämer; Flyer: pdficon pdf ; Thesis: pdficon pdf
    Pictures of the Board during development: From top, From side, LCD
    Pictures of the final Board:LCD with Virtex-II Board, LCD with XUP Virtex-II Pro Board, LCD Wiring
  • Implementierung einer Speicher-Anbindung für einen Eingebetteten Prozessor
    Status: Completed by Tibor Kampeis; Flyer: pdficon pdf ; Thesis: pdficon pdf

Sutdent Assistants (HiWis)