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Research Areas

The Chair for Embedded Systems is devoted to Research in Design and Architectures for Embedded Systems.
A current focus of research are multi-core systems, dependability and low power design.
The Chair has currently the following research groups:

Dependable Hardware
Low Power and Dependability
Adaptive and Self-Organizing On-Chip Systems
Internet of Things

Dependable Hardware

As technology scaling reaches its limit, where displacing a few atoms within a transistor may endanger its entire functionality, the big picture behind aging, degradations, and reliability becomes more complex than often assumed. In our research group, we are the first who explore the instantaneous effects of aging which is a recent discovery that bears a large potential for reliability optimization. Though aging in general is known for a long time and the physical causes behind it such as bias temperature instability (BTI) have been extensively studied in last decade, investigating the impact of instantaneous aging on circuits’ reliability is still in its infancy. Traditionally, aging is treated as a long-term degradation of reliability in which it gradually degrades the chip’s performance over months or years. However, it has been recently reported that the effects of BTI may also be observed in a significantly shorter time domain, i.e. in the order of milliseconds or even microseconds [1, 2].

In our research group, we study different degradations effects (BTI, HCI, RTN, RDF, PV, etc.) from the physical level all the way up to the system level towards providing designers at the systems level with abstracted, yet sufficiently accurate reliability estimations [3, 4]. To achieve that, we collaborate with different international research groups with varied expertise.

Our developed models, software tools and degradation-aware cell libraries are made publicly available allowing other researchers to directly employing them without requiring any further modifications. For more information please visit our research page.

Contact information:
Research Group Leader: Dr.-Ing. Hussam Amrouch, amrouch∂kit.edu

References:
[1] Victor M. van Santen, Hussam Amrouch, Javier Martin-Martinez, Montserrat Nafria, Jörg Henkel “Designing Guardbands for Instantaneous Aging Effects” in ACM/EDAC/IEEE 53rd Design Automation Conference (DAC’16), Austin, TX, USA, June 5-9, 2016 (accepted).
[2] Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel, “Aging-Aware Voltage Scaling” in IEEE/ACM 19th Design, Automation and Test in Europe Conference (DATE’16), Dresden, Germany, pp. 576-581, 2016.
[3] Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel “Reliability-Aware Design to Suppress Aging” in ACM/EDAC/IEEE 53rd Design Automation Conference (DAC’16), Austin, TX, USA, June 5-9, 2016 (accepted).
[4] Hussam Amrouch, Javier Martin-Martinez, Victor van Santen, Miquel Moras, Rosana Rodriguez, Montserrat Nafria and Jörg Henkel, “Connecting the Physical and Application Level Towards Grasping Aging Effects”, in IEEE 53rd International Reliability Physics Symposium (IRPS’15), CA, USA, pp. 3D.1.1-3D.1.8, 2015.

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Low Power and Dependability

 

Infrared thermal image of a chip Advances in technology scaling in the nano-CMOS era have steadily increased the consumed power per chip area (i.e. power density). High power densities are the major reason for unsustainable on-chip temperatures. The trend of technology scaling, with supply voltage scaling reaching its limits, leads to a discontinuation of Dennard Scaling. It may be feasible to only power on a subset of cores at full performance during the same time window. This causes so-called of dark silicon: it mandates that even though a chip may have a plenty of computation and communication resources, it is inevitable to keep some powered off or not running at full performance in order to fulfill chip’s thermal constraints like TDP (Thermal Design Power). Recent research has shown though that the commonly used TDP is too conservative. Advanced measures have been proposed (like “Thermal Save Power”, TSP [1]). Keeping chip temperatures within safe limits is required to also maintain reliability. This is since elevated temperatures negatively influence the lifetime akin to the acceleration of aging mechanisms such as Negative/Positive Bias Temperature Instability (N/PBTI), Hot Carrier Induced Degradation (HCID), Time-Dependent-Dielectric Breakdown (TDDB) etc. State-of-the-art industrial measurements have demonstrated that aging mechanisms simultaneously occur. Thus, recent research has investigated the interdependencies of them and established that looking individually at aging mechanisms results in underestimating their ultimate overall effect [2,3]. Additionally, developing reliable software in the scope of unreliable hardware (e.g., [4]) is also essential. Last but not least, leakage power is exponentially related to the junction temperature. Hence, elevated temperatures directly lead to higher leakage power consumption.

In summary, high power densities and thus elevated temperatures seriously jeopardize the chip’s reliability. Therefore, there is an essential need to develop novel techniques to mitigate the related problems. This is the key focus of this research area at CES (please click here for more details).

 

References:
[1] Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li, Jörg Henkel, "TSP: Thermal Safe Power - Efficient power budgeting for many-core systems in dark silicon", International Conference on Hardware - Software Codesign and System Synthesis (CODES+ISSS), New Delhi, India, pp. 1-10, 2014.
[2] Hussam Amrouch, Victor M. van Santen, Thomas Ebi, Volker Wenzel, Jörg Henkel, "Towards interdependencies of aging mechanisms", IEEE/ACM 33rd International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, pp. 478-485, 2014.
[3] Hussam Amrouch, Javier Martin-Martinez, Victor van Santen, Miquel Moras, Rosana Rodriguez, Montserrat Nafria, Jörg Henkel, "Connecting the Physical and Application Level Towards Grasping Aging Effects", IEEE 53rd International Reliability Physics Symposium (IRPS'15), Monterey, CA, USA, April 2015.
[4] Semeen Rehman, Muhammed Shafique, Florian Kriebel and Jörg Henkel, "Reliable Software for Unreliable Hardware: Embedded Code Generation aiming at Reliability", IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11), Taipei, Taiwan, pp. 237-246, Oct. 2011.

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Adaptive and Self-Organizing On-Chip Systems

Embedded systems are no longer designed and dedicated to a specific and narrow use case. Instead, they are often expected to provide a large degree of flexibility, for instance, users of handhelds can download and start new applications on demand. These requirements can be addressed at different levels for embedded multi-/many core systems, i.e. the processor level and the system level. The main goal of this group is to investigate adaptivity at these levels in order to:

  • increase the performance to fulfill the user's expectations or constraints
  • increase the efficiency, e.g. ‘performance per area' or ‘performance per energy'
  • increase the reliability, i.e. the correct functionality of the system needs to be tested regularly and if
    a component is faulty it needs to be repaired (e.g. by using redundancy) or avoided (i.e. not used any more)

Adaptive-on-chip systemAt the processor level, this group investigates processor microarchitectures (e.g. caches and execution control) and different types of reconfigurable processors (allow changing parts of their hardware at run time). Reconfigurable processors can be realized by hardware structures that are used in FPGAs (field-programmable gate arrays) as they allow changing parts of the FPGA configuration at run time. These run-time reconfigurable processors are often used to provide application-specific accelerators on demand. A run-time system is used to decide which accelerators shall be reconfigured, which is especially challenging in multi-tasking and multi-core scenarios. Run-time reconfiguration can also be used to improve the reliability of a system, which is important in environments with a high radiation (space missions) and for devices that are built using unreliable manufacturing processes (as observed and predicted for upcoming nanometer technology nodes). Here, run-time reconfiguration can help to test the functionality of the underlying hardware, to correct temporary faults, and to adapt to permanents faults. In addition to microarchitectures and run-time systems, also compiler support for reconfigurable processors is investigated to enable a programmer-friendly access to the concepts of reconfigurable processors.

For multi-/many core systems as e.g. Intel's Single-chip Cloud Computer (SCC, providing 48 Pentium-like cores on one chip) or even larger systems, the question arises how these systems can be managed in an efficient way. For instance, the decisions ‘which application obtains how many cores' and ‘on which cores it shall execute' are crucial for performance and efficiency. A run-time system is required that scales with the number of cores and the number of applications that shall execute. Among others, it needs to consider the communication between the applications, the available memory bandwidth, or the temperature of the cores. Strategies that are based on distributed components that negotiate with each other (so-called Agents) are investigated for maintaining scalability and flexibility.

References:
[1] Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel, "RISPP: rotating instruction set processing platform", ACM/IEEE/EDA 44th. Design Automation Conference (DAC'07), San Diego, CA, USA, pp. 791-796. June 2007.
[2] Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel, "Run-time adaptive on-chip communication scheme", IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), San Jose, California, USA, pp. 26-31, Nov. 2007.
[3] Muhammad Shafique, Lars Bauer, Jörg Henkel, "Adaptive Energy Management for Dynamically Reconfigurable Processors", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, Issue 1, pp. 50-63, Jan. 2014.

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Internet of Things

Recent technology advancements and emerging techniques in embedded systems, wireless communication, and sensors have enabled the design of small-size, ultra-low power, and low cost embedded devices which use the Internet as an infrastructure for connecting to each other to communicate, coordinate, compute and cooperate. This novel paradigm is Internet of Things (IoT). IoT is covering a wide range of applications including automotive, smart buildings and, of particular interest, healthcare monitoring [1].

The limited resources on the IoT devices and smart gateways call for novel and application-specific techniques for on-board processing, resource management, offloading schemes, etc [2]. From the embedded perspective, resource-awareness both in hardware platform and software application is necessary in the whole design process and at all abstraction layers. Designing efficient platforms and developing design tools, flows, and methodologies for these devices are some emerging area of research.

In summary, the new paradigm of IoT and particularly, healthcare monitoring systems have brought new challenges and new problems into the embedded design research field. Therefore, new solutions and novel techniques are needed to address these new issues. This is our key focus in this research group at CES.

Contact information:
Farzad Samie (farzad.samie∂kit.edu), Lars Bauer (lars.bauer∂kit.edu).

References:
[1] Farzad Samie, Lars Bauer, Jörg Henkel, “IoT Technologies for Embedded Computing: A Survey”, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IoT day, Pittsburgh, PA, USA, October 2-7, 2016. PDF
[2] Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris, Joerg Henkel, “Distributed QoS Management for Internet of Things under Resource Constraints”, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IoT day, Pittsburgh, PA, USA, October 2-7, 2016. PDF

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Check also: CES PhD Thesis