In the following, you will find free software authored by CES research staff. In addition, there are related publications. They are made available in PDF format for easy access. If you use our software, please refer to the related publication. Note that the relevant copyrights of the paper publications are with organizations like IEEE, ACM, and others.
Design for Reliability
Under the following link you can find our "Degradation-Aware Cell Libraries", our recently physics-based mode for "Instantaneous Aging Effects", our physics-based aging model "Interdependencies of Degradation Effects" which models the joint impact of BTI and HCI aging effects and our "Thermal-Aware Cell Libraries". Our Degradation-Aware Cell Libraries and Thermal-Aware Cell Libraries are fully compatible with existing EDA tool flows such for Synthesis and timing/power analysis. Therefore, they can be used directly without requiring any further modifications.
Available for download at: Dependable Hardware
lpACLib: An Open-Source Library for Low-Power Approximate Computing Modules
“lpACLib” is an open-source library for Low-Power Approximate Computing Modules (like adders and multiplier of different bit-widths) available for download at: https://sourceforge.net/projects/lpaclib/
Verilog/MATLAB based, open-source, approximate adders library
(Generic accuracy configurable adder)
MatEx: Efficient Transient and Peak Temperature Computation for Compact Thermal Models
In many core systems, run-time scheduling decisions, such as task migration, core activations/deactivations, voltage/frequency scaling, etc., are typically used to optimize the resource usages. Such run-time decisions change the power consumption, which can in turn result in transient temperatures much higher than any steady-state scenarios. Therefore, to be thermally safe, it is important to evaluate the transient peaks before making resource management decisions. This paper presents a method for computing these transient peaks in just a few milliseconds, which is suited for run-time usage. This technique works for any compact thermal model consisting in a system of first-order differential equations, for example, RC thermal networks. Instead of using regular numerical methods, our algorithm is based on analytically solving the differential equations using matrix exponentials and linear algebra. This results in a mathematical expression which can easily be analyzed and differentiated to compute the maximum transient temperatures. Moreover, our method can also be used to efficiently compute all transient temperatures for any given time resolution without accuracy losses. We implement our solution as an open-source tool called MatEx. Our experimental evaluations show that the execution time of MatEx for peak temperature computation can be bounded to no more than 2.5 ms for systems with 76 thermal nodes, and to no more than 26.6 ms for systems with 268 thermal nodes, which is three orders of magnitude faster than the state-of-the-art for the same settings.
Santiago Pagani, Jian-Jia Chen, Muhammad Shafique, and Jörg Henkel, "MatEx: Efficient Transient and Peak Temperature Computation for Compact Thermal Models", in Proceedings of the 18th IEEE/ACM Design, Automation & Test in Europe (DATE), Grenoble, France, March 2015.
Thermal Safe Power (TSP)
Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The cooling solution is designed to dissipate this power level. But because TDP is not necessarily the maximum power that can be applied, chips are operated with Dynamic Thermal Management (DTM) techniques. To avoid excessive triggers of DTM, usually, system designers also use TDP as power constraint. However, using a single and constant value as power constraint, e.g., TDP, can result in big performance losses in many-core systems. Having better power budgeting techniques is a major step towards dealing with the dark silicon problem.
This paper presents a new power budget concept, called Thermal Safe Power (TSP), which is an abstraction that provides safe power constraint values as a function of the number of simultaneously operating cores. Executing cores at any power consumption below TSP ensures that DTM is not triggered. TSP can be computed offline for the worst cases, or online for a particular mapping of cores. Our simulations show that using TSP as power constraint results in 50.5% and 14.2% higher average performance, compared to using constant power budgets (both per-chip and per-core) and a boosting technique, respectively. Moreover, TSP results in dark silicon estimations which are more optimistic than estimations using constant power budgets.
Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li, and Jörg Henkel, "TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon", in IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Delhi, India, October 2014.