With limited power/thermal budgets for modern system on chips (SoCs), power minimization has become one of the most important objectives in designing SoCs for various wearable or handheld applications. Higher power dissipation will not only increase system costs but also affect lifetime and reliability. As the process technology advances, applying multi-bit registers becomes promising for minimizing dynamic and leakage power, and hence achieving ultra-low-power design. This talk will introduce some applications of applying multi-bit registers, including clock network minimization, flip-flop state retention due to power gating, and timing/reliability enhancement for time-borrowing and local-boosting error-resilient circuits. The review of the related work and the state-of-the-art design methodologies will also be presented.
Mark Po-Hung Lin received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, respectively, and the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan. He has been with the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan, since 2009, where he is currently an Associate Professor. He was with SpringSoft, Inc. (acquired by Synopsys in 2012) during 2000–2007 as an Engineer, a Senior Engineer, an Associate Manager, and a Technical Manager. He was a Visiting Scholar with the University of Illinois at Urbana-Champaign, Champaign, IL, USA, during 2007–2009, and a Humboldt Research Fellow with the Technical University of Munich (TUM), Germany, during 2013–2015. His current research interests include low-power circuit and system design optimization, and design automation for analog/mixed-signal integrated circuits. Dr. Lin was the recipient of Humboldt Research Fellowship for Experienced Researchers, IEEE Tainan Section Macronix Award, IEEE Tainan Section Best GOLD Member Award, Distinguished Young Scholar Award of Taiwan IC Design Society, Outstanding Young Electrical Engineer Award of the Chinese Institute of Electrical Engineering, and Distinguished Young Faculty Award of National Chung Cheng University.
Low-Power Circuit Optimization with Multi-Bit Registers
Assistant Prof. Mark Po-Hung Lin
National Chung Cheng University, Chiayi, Taiwan
|Date:||Aug. 4th, 13:00|