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IEEE Design&Test Vol.33, Issue 6 (November/December) is released: Best in Test

IEEE Design&Test Vol.33, Issue 6 (November/December) is released: Best in Test
Date: October 28th 2016
Design & Test

Magazine
Volume 33, Issue 6 (November/December 2016)

Highlights


Special Issue on "Best in Test"
 

The 2016 DAC Art Show Winner: Misha Temkin (Free Access)
 

November/December 2016 Content


From the EIC
Best in Test
  View full article (PDF) here.

Best in Test
Guest Editors' Introduction: Top Papers from the 2015 International Test Conference
  View full article (PDF) here.
On New Test Points for Compact Cell-Aware Tests
  Test points are known to improve the fault coverage in BIST applications. This article discusses a new class of ... read more.
View full article (PDF) here.
An ATE System for Testing RF Digital Communication Devices With QAM Signal Interfaces
  The capital cost of conventional RF ATE systems is very high. This article presents a low-cost ATE system that is ... read more.
View full article (PDF) here.
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC
  Online monitoring of interconnect delay is important for early detection of reliability hazards, especially in multidie ICs. This article ... read more.
View full article (PDF) here.
Practical Application of RAM Sequential Test
  With the growing number and speed of embedded memories, testing for delay defects in the logic surrounding RAMs is becoming ... read more.
View full article (PDF) here.
Streaming Access to ADCs and DACs for Mixed-Signal ATPG
  This article proposes a small digital circuit that can be added to each ADC/DAC parallel port to provide ... read more.
View full article (PDF) here.
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques
  Accurate and efficient evaluation of alternative test methods is required for analog/mixed-signal circuits. To address this need, ... read more.
View full article (PDF) here.
Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions
  Reducing the error detection latency is critical for improving the design visibility while searching for design errors. This article uses ... read more.
View full article (PDF) here.

General Interest Papers
Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again
  This article addresses the problem of nondeterminism due to design optimization such as resetting ... read more.
View full article (PDF) here.
Power Delivery Performance of Probe Test Systems for Semiconductor Wafers
  The focus of this article is on power delivery of probe testers for wafers. When the interconnect design is optimized, ... read more.
View full article (PDF) here.
FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories
  In this article, the authors implement an FPGA simulator that accelerates the performance evaluation of very long QC-LDPC codes, and present ... read more.
View full article (PDF) here.
CIRCA-GPUs: Increasing Instruction Reuse Through Inexact Computing in GP-GPUs
  The authors introduce a method that exploits fine-grained parallelism and approximate computing in GP-GPU architecture to ... read more.
View full article (PDF) here.

Departments
Recap of the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016)
  Access Article (PDF) here.
The 2016 DAC Art Show Winner: Misha Temkin
  Free Access Article (PDF) here.
ITC and the Future of Test — We've Won
  Free Access Article (PDF) here.

 

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