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IEEE Design&Test Vol.34, Issue 1 (January/February) released: Special Issue on 3D-Test

IEEE Design&Test Vol.34, Issue 1 (January/February) released: Special Issue on 3D-Test
Date: January 17th 2017
Design & Test

Magazine
Volume 34, Issue 1 (January/February)

Highlights
Special Issue on "3D-Test"  
Perspective by Mark Papermaster, "Developing Great Products for the Immersive Computing Era"
Tutorial by Andy D. Pimentel, "Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration"

January/February 2017 Content


From the EIC
3D Test
  View full article (PDF) here.

3D-Test
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory
  View full article (PDF) here.
Unleashing Fury: A New Paradigm for 3-D Design and Test
  This paper, based on an excellent keynote address by AMD's Jeff Rearick at 3D-TEST 2015, describes ... read more.
View full article (PDF) here.
High-Bandwidth Memory (HBM) Test Challenges and Solutions
  TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by ... read more.
View full article (PDF) here.
High-Performance HBM Known-Good-Stack Testing
  Based on Loranger's talk at 3D-TEST 2015, this article details the dedicated developments performed at probe-card supplier ... read more.
View full article (PDF) here.

General Interest Papers
Estimating the Impact of Methodology on Analog Integrated Circuit Design Time
  The article discusses analog design practices and proposes a project management model for studying ... read more.
View full article (PDF) here.
Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias
  Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes ... read more.
View full article (PDF) here.
A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications
  Testability is a perennial concern that requires ever-improved solutions; however, potentially resultant security vulnerabilities ... read more.
View full article (PDF) here.
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms
  Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents ... read more.
View full article (PDF) here.

Departments
Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration
  Access Article (PDF) here.
Developing Great Products for the Immersive Computing Era
  Access Article (PDF) here.
An Interview With Semiconductor Pioneer and EDA Visionary Leader Wally Rhines
  Free Access Article (PDF) here.
Report of the 2016 Embedded Systems Week (ESWEEK)
  Free Access Article (PDF) here.
The 2016 DAC Art Show Grand Prize Winner: Coventor, Inc.
  Free Access Article (PDF) here.
Research Is Its Own Reward
  Free Access Article (PDF) here.

 

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