For almost 20 years the power wall of IC integration of high end (HPC) digital systems has been contended with. This wall arises from basic thermal and power density considerations on silicon materials and devices. New circuit design techniques are being explored in the other direction, i.e. research towards the power-bottom floor, where CMOS is still an unbeatable and flexible technology to make the internet of “everything” possible and cost-effective.
In this Seminar we present IC design cases on applying approximate computing in the domain of digital audio filtering, image filters for edge detection, and on video coding operators, all targeting low power dedicated architectures. The energy consumption vs. accuracy trade-offs will be presented for at least 3 of such applications. At the other end, on the realm of any application which can tolerate very wide voltage-frequency scaling (VFS), the Seminar will address performance vs. energy efficiency trade-offs in the design of the VLSI digital circuits for the Internet-of-Things (IoT) hardware. These circuits operate at very different power-performance modes, from sub-MHz to peaks of hundreds of MHz, for the digital part.
This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS, and targets near-threshold operation for best energy-efficiency. The results in CMOS circuit design are obtained using the minimal cycle time achievable at each supply voltage, down to very low 200 mV supplies, providing insights on valuable temperature effects on circuit performance and efficiency.
Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute, member of the faculty since 1986. He served as Graduate Program Coordinator (2003-2007), head of research group and projects, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff, and a visiting research faculty at Stanford University (1998-99) in the USA.
His research interests are in the area of IC design, ultra-low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing, nano-CMOS devices, mixed signal and RF CMOS design for IoT.
He has co-authored more than 340 papers in these fields and in MOS devices and EDA.
He is a senior member of IEEE, SBC, and SBMICRO societies. He was Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshop.