The last decade has witnessed the emergence of the Application Specific Instructionset Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with Instruction Set Extensions (ISEs) that execute on Application Specific Functional Units (AFUs) － dedicated hardware that executes the ISEs. Due to the limited number of read and write ports in the register file of the base processor, the size and complexity of AFUs are generally limited. Recent work has focused on overcoming these constraints by serialising access to the register file. Apart from these complications, the primary challenge in the identification and selection of the best AFU is the modelling of AFU performance in the context of different base processors: once the base processor changes, the ISE identification and AFU selection process must be redone from scratch. Exhaustive ISE/AFU enumeration methods are not scalable and generally fail for larger applications. To address this concern, a new approach to ISE/AFU identification is proposed. In particular, we show that the speedup model of ISEs/AFUs is independent of the specific details of the base processor, under fairly reasonable assumptions. The approach presented here significantly prunes the list of best ISE/AFU candidates compared to previous approaches. Experimentally, we observe the new approach produces optimal results on larger applications where prior approaches either fail or produce inferior results.
Bio Dr. Philip Brisk:
Philip Brisk received his BS, MS, and PhD degrees, all in computer science, from UCLA in 2002, 2003, and 2006 respectively. He is currently a postdoctoral researcher in the processor architecture laboratory at EPFL. His current research interests include compilers, customizable processors, and FPGA architectures, as well as other related topics. He was a co-author of a paper that received the best paper award at CASES, 2007.