Abstract:
During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyzer. In order to reduce the transfer time and save expensive logic analyzer memory, we propose to compress the cache contents on their way out. We present a hardware compression engine for cache data using a Cache Aware Compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression. Dumping of cache state could also be carried out online, while permitting the CPU to execute simultaneously. Experimental results indicate that the technique results in 7-31% better compression than one that treats the data as just one long bit stream.

Short Bio:
Preeti Ranjan Panda received his B. Tech. in CSE from IIT Madras in 1990, and his M. S. Ph.D. in Info. & CS from the University of California at Irvine in 1995 and 1997 respectively. He is currently an Associate Professor in the Dept. of CSE at IIT Delhi. He has previously worked at Texas Instruments, Bangalore and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University (1999-2000). His research interestsare: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, and Low Power Design. He is the author of the book Memory issues in Embedded Systems-on-chip: Optimizations and Exploration, Kluwer Academic Publishers. He is a recipient of an IBM Faculty Award (2007) and a Department of Science and Technology Young Scientist Award (2003). He has served on the program committees and chaired sessions at several conferences in the areas of CAD/VLSI and Embedded Systems: ICCAD, DATE, ASPDAC, CODES/ISSS, etc. He is a member of the editorial board of ACM TODAES and International Journal of Parallel Programming.