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Variation-Aware Instruction Set Architecture Synthesis

Variation-Aware Instruction Set Architecture Synthesis
Dr. Yuko Hara-Azumi

Ritsumeikan University, Japan


H120, Technologiefabrik

Date: Friday, April 13th, 9:30

As the process variation is growing, the traditional deterministic worst-case approach is now too pessimistic, and stochastic approaches (e.g., statistical static timing analysis (SSTA)) are being introduced at both HW and SW levels. In this talk, I will present my current work on variation-aware instruction set architecture (ISA) synthesis, which is collaboration with Prof. Nikil Dutt at University of California, Irvine. To the best of our knowledge, this work is the first attempt on ISA synthesis to tackle the process variation comprehensively from both HW and SW points of view; on the HW side, a Razor-like processor (originally proposed for low power design) dynamically detects and corrects timing faults with minimum performance degradation (i.e., stalls); furthermore, on the SW side, custom instructions are applied based on SSTA so that an efficient speedup of the application is achieved without yield degradation. 

Yuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. She was a visiting scholar at University of California, Irvine, in 2010 and 2011-2012. Currently she is a research fellow of the Japan Society for the Promotion of Science at Ritsumeikan University, and is supposed to become an assistant professor of Nara Institute of Science and Technology (NAIST) from this June. Her research interests include system-level design methodology for dependable systems and embedded systems, especially on high-level and logic synthesis, ISA synthesis, and biochips.