Compilation for STT-RAM based Hybrid Cache in Embedded Systems

Abstract:
SRAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most work on hybrid caches employs migration based strategies to dynamically move write-intensive data from STT-RAM to SRAM. Migrations require additional read and write operations for data movement and may lead to significant overheads. To address this issue, this paper proposes two compilation methods, Migration-aware Data Layout (MDL) and Migration-aware Cache Locking (MCL), to improve the energy efficiency and performance of STT-RAM based hybrid cache. These two methods can change the data access pattern in memory blocks in a way that the migration overhead is reduced without any hardware modification.