A threshold function is a Boolean function that can be expressed as an arithmetic predicate involving a weighted linear sum of the inputs. Threshold functions are a proper subset of unate Boolean functions. A threshold gate is a primitive, non-decomposable, multi-input, single-output cell that realizes a threshold function. Such a gate can realize a complex Boolean function, which would otherwise require a multi-level network when implemented using conventional logic primitives. Since the traditional primitive logic functions such as AND/OR are threshold functions, a Boolean function represented as a multi-level network of such primitives can be viewed as a special case of a threshold network. However, since threshold functions can be much more complex functions than the standard logic primitives, a conventional logic network when decomposed into a multi-level network of threshold gates can lead to significant improvement in power, area and/or performance.
This presentation will describe the main ingredients for transforming a Boolean network into hybrid network of threshold gates and conventional logic gates: (1) the design of a robust, compact differential mode logic circuit that realizes a threshold gate, (2) the enumeration of threshold logic cells in the form of a standard cell library, (3) fast procedures for identifying a threshold function, and (4) methods for systematically exploring a general sequential logic network to replace sub-circuits with threshold gates.
Sarma Vrudhula is a Professor in the School of Computing, Informatics and Decisions Systems Engineering at Arizona State University, and the Director of the NSF I/UCRC Center for Embedded Systems. He received the Bachelor of Mathematics from the University of Waterloo, Ontario, Canada, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California.
Dr. Vrudhula’s research work is in VLSI design automation and CAD with a focus on improving the power consumption and energy efficiency of digital systems. His research has covered new circuit architectures for low power, logic synthesis and optimization, system level dynamic power and thermal management of multicore processors, energy optimization of battery powered computing systems and wireless sensor networks, models and methods for the analysis and optimization of power and performance in the presence of process variations.