At submicron manufacturing technology nodes, process variations affect circuit performance significantly. This trend usually leads to a large timing margin to maintain yield. To combat this pessimism, post‐silicon clock tuning can be applied to improve yield by balancing timing budgets of critical paths in chips after manufacturing. In this talk, a method to determine the number and locations of clock tuning components is presented. For tuning chips after manufacturing, a postsilicon test strategy is also introduced. Furthermore, the concept of balancing timing budgets between combinational paths across flip‐flop stages is generalized in a new design view, where flipflops are inserted only on paths that are too fast, so that the penalty imposed by the delays of flipflops and their setup time onto critical paths can be removed. This new design view also enables a further protection of circuit netlists from counterfeiting, because the function of a circuit is thus defined not only by its netlist, but also by the timing information to maintain multiple logic waves propagating along combinational paths simultaneously.
Dr.‐Ing. Bing Li received the bachelor’s and master’s degrees in communication and information engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 2000 and 2003, respectively, and the Dr.‐Ing. degree in electrical engineering from Technical University of Munich (TUM), Munich, Germany, in 2010. He is currently a researcher with the Chair of Electronic Design Automation, TUM. His research interests include high‐performance and lower‐power design, as well as emerging systems. He has served on technical program committees of several conferences such as ICCAD, DATE and ASP‐DAC.