Long-term reliability such as electromigration (EM) is the key failure mechanisms for copper-based damascene interconnect wires for current and future sub-10nm technologies. 2015 ITRS predicts that EM lifetime of interconnects of VLSI chips will be reduced by half for each generation of technology nodes. As a result, the semiconductor industry will soon confront the reliability crisis down the road if no transformative mitigation techniques are provided. In this talk, I will present some of recent research works in my research lab (VSCLAB) at UC Riverside. First, I will review a recently proposed physics-based three-phase EM models for multi-segment interconnect wires, which consists of nucleation, incubation and growth phases to completely model the EM failure processes in typical copper damascene interconnects. The new EM model can predict more accurate EM failure behaviors for multi-segment wires such as interconnects with reservoir and sink segments. Second, we will present newly proposed fast aging acceleration techniques for efficient EM failure detections and validation of practical VLSI chips. Different from the traditional temperature and current-density based EM acceleration techniques, the new method is based on the observation that reservoir and sink structures have significant impacts on the lifetime of multi-segment interconnect wires. I will then present the novel configurable reservoir/sink-structured interconnect designs in which the current in the sink segment can be activated/deactivated dynamically during operation. In this way, the stress conditions of the interconnect wires can be increased and the lifetime of the wires can be reduced significantly. Our study shows that by combining with limited temperature-based acceleration (up to 150C), one can for the first time achieve the lifetime reduction from 10 years to a few hours while staying within the feasible operating zones of chips. Last, not least, I will present a fast 2D stress numerical analysis technique based on the Krylov subspace and finite difference time domain methods (FDTD) for general interconnect wires structure. The proposed numerical analysis method can lead to 100X speedup over the simple FDTD method and can be applied to any interconnect structures for all the EM wear-out phases.
Dr. Sheldon Tan is a Professor in the Department of Electrical Engineering, University of California, Riverside, CA. He is the Associate Director of Compute Engineering Program (CEN) and cooperative faculty member in the Department of Computer Science and Engineering at UCR. Dr. Sheldon Tan received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. He is a visiting professor of Kyoto University as a JSPS Fellow since Dec. 2017. His research interests include VLSI long-term reliability, resilient systems, fault tolerant computing, reliability-aware design and management at circuit and system levels; parallel and intelligent computing (deep learning) and analysis on heterogeneous and accelerator-rich (GPUs) platforms; hardware security and trust computing; smart devices and embedded and cyber-physical systems; thermal modeling, optimization and dynamic thermal management at circuit, chip and board levels; statistical modeling and optimization for VLSI systems.
Dr. Tan received the Best Paper Award from DAC in 1999 and the Best Paper Award from ICCD 2007. He also received Best Paper Award nominations from DAC’05, DAC’09, DAC’14 and ASPDAC’15. Dr. Tan received NSF CAREER Award in 2004. He has co-authored four books and over 240 publications. He is now the Editor in Chief for Integration, The VLSI Journal (Elsevier) since 2016, He is also serving as an Associate Editor for three journals: IEEE Transaction on VLSI Systems (TVLSI), ACM Transaction on Design Automation of Electronic Systems (TODAE) and Microelectronics Reliability (Elsevier).