We propose an efficient Ising processor with approximated parallel tempering (IPAPT) implemented on an FPGA. Hardware-friendly approximations of the components of parallel tempering (PT) are proposed to enhance solution quality with low hardware overhead. Multiple replicas of Ising states having different temperatures run in parallel by sharing a single network structure, and the replicas are exchanged based on the approximated energy evaluation. The application of PT substantially improves the quality of optimization solutions. The experimental results on the various max-cut problems have shown that utilization of PT significantly increases the probability of obtaining optimal solutions, and IPAPT obtains optimal solutions two orders magnitude faster than a software solver.
Takashi Sato obtained his Ph.D at Kyoto University in informatics. He was with Hitachi, Ltd., Tokyo, Japan from 1991 to 2003, with Renesas Technology Corp., Tokyo, Japan from 2003 to 2006, and with Tokyo Institute of Technology, Yokohama, Japan. In 2009, he joined the Graduate School of informatics, Kyoto University, Kyoto, Japan, where he is currently a professor. He was a visiting industrial fellow at the University of California, Berkeley from 1998 to 1999. His research interests include modeling and CAD for nanometer-scale circuit design, fabrication-aware design methodology, and performance optimization for variation tolerance. Dr. Sato is a member of IEEE, the Association for Computing Machinery (ACM), and Institute of Electronics, Information and Communication Engineers.