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IEEE Design&Test Vol. 36, Issue 3

IEEE Design&Test Vol. 36, Issue 3
Speaker:
Architecture Advances Enabled by Emerging Technologies
Location:

IEEE Explorer

Date: May/June
Design & Test

Magazine
Volume 36, Issue 3 (May/June)

Highlights
Special Section on "Architecture Advances Enabled by Emerging Technologies"
General Interest Paper by Jae Woong Jeong, Jennifer Kitchen, and Sule Ozev "On-Chip RF Phased Array Characterization with DC-Only Measurements for In-Field Calibration"

May/June 2019 Content


From the EIC
Architecture Advances Enabled by Emerging Technologies
  View full article (PDF).

Special Issue on Architecture Advances Enabled by Emerging Technologies
Guest Editors’ Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies
  As we approach the twilight of Moore’s Law and dimensional scaling of advanced CMOS technologies, many beyond-CMOS logic and memory device technologies are being explored. In order to fully exploit the promises of these emerging technologies, we need major simultaneous advances in architecture and design, especially for the new computing workloads in future intelligent IoT systems. This special issue presents five articles that describe emerging opportunities for such technologydesign- architecture co-optimizations.
View full article (PDF).
Computing with High-Dimensional Vectors
  Editor's note: The author reviews the principles of high-dimensional (HD) computing as a brain-inspired paradigm, with variables and operations encoded in vectors with high dimensionality (e.g., 10,000). read more.
View full article (PDF).
Voltage-Driven Building Block for Hardware Belief Networks
  Editor's note: In this article, the authors present a hardware building block for probabilistic spin logic (PSL) consisting of a probabilistic bit (p-bit) made from an embedded low-barrier unstable magnetic tunnel junction (MTJ) and a capacitive voltage adder. read more.
View full article (PDF).
Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications
  Editor's note: This article proposes a reconfigurable logic family comprised of spin-based devices that may be dynamically configured/reconfigured owing the versatility of the giant spin-Hall effect (GSHE) device. read more.
View full article (PDF).
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures
  Editor's note: In this article, the authors present a circuit-level macro model (“NeuroSim” simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. read more.
View full article (PDF).
Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs
  Editor's note: This article explores the design of high-density, low-power, and high-speed embedded nonvolatile memory arrays exploiting the unique device characteristics of the emerging ferroelectric FETs read more.
View full article (PDF).

Survey Papers
A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies
  Editor's note: Emerging non-CMOS devices have various advantages and challenges. It is important to undertake device-architecture codesign to harness the true benefits of beyond-CMOS devices. read more
View full article (PDF).
A Survey on Security Threats and Countermeasures in IEEE Test Standards
  Editor's note: Test infrastructure has been shown to be a portal for hackers. read more
View full article (PDF).

General Interest Papers
On-Chip RF Phased Array Characterization with DC-Only Measurements for In-Field Calibration
  Editor's note: This article presents an on-chip built-in self-test (BIST) measurement system for in-field calibration of RF phased arrays. read more
View full article (PDF).
 
Departments
Quantum Computing Circuits and Devices
  View full article (PDF).
System Testing Ourselves
  View full article (PDF).