There have been many issues in synthesizing analog cell and circuit layouts. In this talk, I will brief some of our current efforts in this direction: to close the gap between pre-simulation and post-simulation results in nanometer analog layouts, analog placement considering current flow and symmetry constraints, and P&R of customized peripheral circuits in IoT SRAM system. With this talk, I hope to shed some light on these still-not-well-solved problems, and discuss the future application on beyond-10nm cell library layout synthesis.
Dr. Chen is currently a Professor in the Institute of Electronics at National Chiao Tung University, Hsinchu, Taiwan. He has served as the chair of IEEE CEDA Taipei Chapter and the technical program committee members including ACM/IEEE ASP-DAC, IEEE/ACM ICCAD and ACM ISPD. He also served as EDA track co-chair in IEEE VLSI-DAT since 2015. He has supervised a team to win the first place at 2014 ISPD Placement Contest. His research interests include design automation in digital and analog circuits, beyond-die integration, and VLSI design methodologies.