Chair for Embedded Systems

IEEE Design&Test Vol. 37, Issue 3

  • Speaker:
    Image Processing, Correspondsing Hardware Architectures, and EDA Tools
  • Location:

    IEEE Explorer

  • Date: May/June
Design & Test

Magazine
Volume 37, Issue 3 (May/June)

Highlights
Special Issue on "SBCCI 2018"
Tutorial by Tamzidul Hoque, Rajat Subhra Chakraborty, and Swarup Bhunia  "Hardware Obfuscation and Logic Locking: A Tutorial Introduction"
General Interest Paper by Shaoyi Peng and Sheldon X.-D. Tan "GLU3.0: Fast GPU-Based Parallel Sparse LU Factorization for Circuit Simulation"
General Interest Paper by Georgia-Irene Trouli and George Kornaros "Automotive Virtual In-Sensor Analytics for Securing Vehicular Communication"

May/June 2020 Content


From the EIC
Image Processing, Correspondsing Hardware Architectures, and EDA Tools
  View full article (PDF).

Special Issue SBCCI 2018
SBCCI 2018
  View full article (PDF).
High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction
  High Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is a video compression standard. An efficient hardware for 3D-HEVC depth-map intraprediction is discussed in the article. read more
View full article (PDF).
Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction
  The usage of multicore architectures for 3D-HEVC intraframe prediction is of great benefit, especially to improve the performance, throughput, and even the energy consumption in systems. read more.
View full article (PDF).
High-Throughput Hardware Design for 3D-HEVC Disparity Estimation
  Disparity refers to the fact, that, for example, human beings see an object from a different angle with the left eye and the right eye. read more.
View full article (PDF).
Hardware-Based Fast Hybrid Morphological Reconstruction
  The optimized hybrid (FH) morphological reconstruction algorithm used in image analysis with FPGA and ASIC implementation is discussed in this article. read more
View full article (PDF).
Optimal Energy Efficiency and Throughput on Partially Reversible Pipelined QCA Circuits
  The low-power aspects for Quantum-dot Cellular Automata (QCA) devices are evaluated and discussed. read more
View full article (PDF).
Exact Benchmark Circuits for Logic Synthesis
  The benchmarking of hardware and its comparison to a golden model is an interesting approach for developers and scientists to align their own results to optimal solutions. read more
View full article (PDF).

General Interest Papers
GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation
  Many scientific computing problems, including circuit simulations, rely on efficient lower–upper (LU) decomposition of sparse matrices. read more
View full article (PDF).
Automotive Virtual In-sensor Analytics for Securing Vehicular Communication
  Resistive crossbar arrays are promising options for accelerating enormous computation needed for training modern deep neural networks (DNNs). read more
View full article (PDF).

Tutorial Paper
Hardware Obfuscation and Logic Locking: A Tutorial Introduction
  If you are designing or integrating hardware IP blocks into your designs, and you are using common global supply chains, then reading this overview article on how to protect your IP against reverse engineering, piracy, and malicious alteration attacks is a must. read more
View full article (PDF).

Departments
2019 DAC Roundtable
  View full article (PDF).
Holding Conferences Online due to COVID-19: The DATE Experience
  View full article (PDF).
ASPLOS Report
  View full article (PDF).
The Last Byte: 3-D TV? We Got 6-D TV!
  View full article (PDF).