This package consists of our toolchain and example application compiled versions with distinct reliability and performance properties. Our toolchain contains a Configurable Fault Generator integrated with a Reliability-Aware Processor Simulator, Fault Injector and Error Logger for analyzing the impacts of (single and multiple) bit flips in different processor components on the application execution. The faults are injected in hardware components and the error analysis is done at the application level. Based on a processor description and environmental parameters the Configurable Fault Generator creates fault scenarios which are the basis for the subsequent fault injection by the Reliability-Aware Processor Simulator. It simulates the application under fault conditions and keeps track of the high-level processor status for every cycle along with the application output and its termination information which can be used for classifying the impacts of faults on different applications. Further details can be found in our following CODES+ISSS'11 paper.
Citation: In case of usage, please refer to our corresponding CODES+ISSS 2011 publication:
Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel, "Reliable Software for Unreliable Hardware: Embedded Code Generation aiming at Reliability", IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Taipei, Taiwan, October 2011, pp. 237-246.