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IEEE Design&Test Vol. 34, Issue 5

IEEE Design&Test Vol. 34, Issue 5
Speaker:
Special Issue on Emerging Challenges and Solutions in SoC Verification
Location:
IEEE Explorer
Date: September/October
Design & Test

Magazine
Volume 34, Issue 5 (September/October)

Highlights
Special Issue on "Emerging Challenges and Solutions in SoC Verification"
Perspective by Francky Catthoor, Guido Groeseneken, "Will Chips of the Future Learn How to Feel Pain and Cure Themselves?"  
Call for Contributions Special Issue on Architecture Advances Enabled by Emerging Technologies  
"An Interview With Professor Chenming Hu, Father of 3D Transistors" by Yao-Wen Chang  
Book Review by Scott Davidson, "Engineering Secure Internet of Things Systems"

September/October 2017 Content


From the EIC
Verification and Test
  View full article (PDF).

Emerging Challenges and Solutions in SoC Verification
Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification
  View full article (PDF).
Challenges and Trends in Modern SoC Design Verification
  This paper provides a tutorial overview of the state-of-the-art in verification of complex and heterogeneous Systems-on-Chip... read more
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Data-Driven Test Plan Augmentation for Platform Verification
  This article points out that the fundamental problem of platform verification is incompleteness of the test plan and proposes an unsupervised learning approach to augment the test plan ... read more
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Formally Verifying Transfer Functions of Linear Analog Circuits
  This article presents an approach to extend mathematical formal analysis towards verification of linear analog circuits... read more.
View full article (PDF).
Embedded Systems Secure Path Verification at the Hardware/Software Interface
  The article presents a case study comparing two types of properties for formal verification of security requirements in embedded systems... read more
View full article (PDF).
Leveraging Software Configuration Management in Automated RTL Design Debug
  This article presents an enhancement to the existing automated debugging software by leveraging statistics from the revision control history... read more
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Formal-Based Design and Verification of SoC Arbitration Protocols: A Comparative Analysis of TDMA and Round-Robin
  As System-On-Chips (SoCs) Are increasing in size and complexity, their validation and verification have become important and more difficult to achieve. Currently, the most widely used SoC design is typically bus based... read more
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Keynote Paper
Probing Attacks on Integrated Circuits: Challenges and Research Opportunities
  As a type of invasive physical attacks, probing attacks are able to access and directly monitor security critical nets of an IC and extract sensitive information. In this paper, the authors summarize the state-of-the-art probing and anti-probing technologies and their challenges, and discuss the opportunities in the relevant research. read more
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General Interest Papers
Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits
  2.5-D integrated circuit (IC) is a cost-efficient alternative to through-silicon-via (TSV)-based 3-D IC. In this paper, the authors give a comprehensive summary of the testing challenges of 2.5-D ICs and their existing solutions... read more
View full article (PDF).

Departments
Will Chips of the Future Learn How to Feel Pain and Cure Themselves?
  View full article (PDF).
Call for Contributions Special Issue on Architecture Advances Enabled by Emerging Technologies
  Free Access Article (PDF).
An Interview With Professor Chenming Hu, Father of 3D Transistors
  Free Access Article (PDF).
Engineering Secure Internet of Things Systems
  Free Access Article (PDF).
To Verification Infinity and Beyond
  Free Access Article (PDF).

 

Table-of-Contents