Near-threshold computing in CMOS is a promising alternative for any application which can tolerate very wide voltage-frequency scaling (VFS). Internet-of-Things (IoT) devices will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific design and management techniques to be applied in systems-on-chip. This talk addresses a method to design CMOS circuits for a wide dynamic range of VFS, and targets near-threshold for best energy-efficiency. A standard-cell based design methodology specific for near-VT is demonstrated for a commercial 65nm CMOS process. Power and timing variability are characterized, so that variation-aware and yet ultra-low supply voltage designs are enabled. Our cell design method avoids unnecessary area upsizing and it focus on near- and well above threshold regions of operation. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) our work demonstrates 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each supply voltage, down to 0.2V supplies.
The extremely low and highly-variable performance and static power at sub- and near-VT have to be addressed by new logic design paradigms. In this talk we also exploit the use of approximate adders to increase the timing performance of a class of digital filter circuits, for audio and image processing, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19% and 37% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our approximate adder design method enables higher levels of energy efficiency in CMOS VLSI for visual/perceptual applications.
Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), Brazil, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Architecture and Microelectronics fields at UFRGS, at the Informatics Institute since 1986. He directs research in the Microelectronics and Computer Science Programs at UFRGS since 1988. He served as the technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2004). His research interests are in the area of IC design, nano-CMOS devices, mixed signal and RF CMOS design, low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing. He has co-authored more than 200 papers in these fields and in MOS devices and EDA. He is a member of IEEE, ACM, SBMICRO scientific societies. He was the Distinguished Lecturer or IEEE CAS 2010-2011,Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshop, and track Chair of several conferences.