The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. Accordingly, with demanding resource constraints, design time techniques per se are less likely to ensure power integrity. Recently several works have shed light on the possibilities of runtime noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume, either implicitly or explicitly, that the placement of the sensors is given. It remains an open problem how to optimally place a given number of noise sensors for best voltage emergency detection. A seemingly relevant problem is the temperature sensor placement, which has been well studied in literature. We then ask: is our problem a trivial extension, or does it present new challenges?
In this talk, we formally define the problem of noise sensor placement and reveal its fundamental difference from the temperature sensor placement. The problem itself is NP-hard, and we put forward an efficient algorithm to solve it. Interestingly, we are able to prove that the algorithm is optimal in the class of polynomial complexity approximations. We conclude our talk with experimental results on a set of industrial power grid designs, which show significant reduction in the miss rate of voltage emergency detections.
Dr. Yiyu Shi is currently an associate professor in the Department of Computer Science and Engineering and Electrical Engineering (concurrent appointment) at the University of Notre Dame. He received his B.S. degree (with honor) in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. He was an assistant professor in the Electrical and Computer Engineering Department at Missouri University of Science and Technology from 2010 to 2015, where he was the site founding co-director of the NSF I/UCRC Net-Centric Software and Systems Center. His current research interests include low-power design, three-dimensional integration, hardware security and renewable energy applications. In recognition of his research, eight of his papers have been nominated for the Best Paper Award and one paper have received the Best Paper in Track, all in top conferences (DAC'05, ICCAD'07, ICCD'08, ASPDAC'09, DAC'09, ISPD'13, ICCAD'14, ISPD'15, DAC'16). He was also the recipient of IBM Invention Achievement Award in 2009, Japan Society for the Promotion of Science (JSPS) Faculty Invitation Fellowship, Humboldt Research Fellowship, IEEE St. Louis Section Outstanding Educator Award, Academy of Science (St. Louis) Innovation Award, Missouri S&T Faculty Excellence Award, NSF CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, all in 2014, and the Air Force Summer Faculty Fellowship in 2015 and 2016. He has served on the technical program committee of many international conferences including DAC, ICCAD, DATE, ISPD, ASPDAC and ICCD. He is also on the editorial board of IEEE TCAD, ACM JETC, VLSI Integration, IEEE VLSI CAS Newsletter, IEEE TCCCPS Newsletter and ACM SIGDA Newsletter. He is a senior member of IEEE.