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IEEE Design&Test Vol. 33, Issue 3 (May/June) is released

IEEE Design&Test Vol. 33, Issue 3 (May/June) is released
Date: May 5th 2016
Design & Test

Magazine
Volume 33, Issue 3 (May/June 2016)

Highlights
Special Issue on "Robust 3-D Stacked ICs"  
Perspective by Andres Takach, Mentor Graphics, on "High-Level Synthesis: Status, Trends, and Future Directions" (Free Access)
"The 3-D Interconnect Landscape" by Eric Byne, IMEC
Interview by Gabe Moretti on "Accellera's DVCon Conferences Focus on the Community of Practicing Engineers"
Tutorial on "Toward Silicon-Based Cognitive Neuromorphic ICs — A Survey"  
Tutorial on "PUFs as Promising Tools for Security in Internet of Things" (Free Access)  

May/June 2016 Content


From the EIC
Robustness for 3-D Circuits — Industrial Perspectives
  View full article (PDF) here.

Robust 3-D Stacked ICs
Guest Editors' Introduction: Robust 3-D Stacked ICs
  View full article (PDF) here.
The 3-D Interconnect Technology Landscap
  This overview article sheds light into the diverse notions and terms associated with 3-D circuits. It categorizes and classifies the various technologies/techniques and helps ... read more.
View full article (PDF) here.
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits
  This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents ... read more.
View full article (PDF) here.
Reliability Challenges Related to TSV Integration and 3-D Stacking
  This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions ... read more.
View full article (PDF) here.
Innovative Failure Analysis Techniques for 3-D Packaging Developments
  Physical failure analysis (PFA) gives unparalleled insight into the nature of microelectronic structures and their defects. Developments in 3-D integration and packaging techniques ... read more.
View full article (PDF) here.

General Interest Papers
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components
  The authors describe how heterogeneity in on-chip components can yield a high overall efficiency that goes beyond of what Moore’s Law promises ... read more.
View full article (PDF) here.
Designing a Cyber-Physical System for Fall Prevention by Cortico-Muscular Coupling Detection
  The authors present wearable noninvasive electronics that prevent a human from falling. It deducts a probable fall from EEG and EMG information ... read more.
View full article (PDF) here.
Real-Time Fault Detection and Diagnosis System for Analog and Mixed-Signal Circuits of Acousto — Magnetic EAS Devices
  The paper discusses fault diagnosis of the electronic circuit board, part of acousto–magnetic electronic article surveillance detection devices. The aim is that the end-user can run the fault diagnosis in real time ... read more.
View full article (PDF) here.

Departments
Toward Silicon-Based Cognitive Neuromorphic ICs — A Survey
  Access Article (PDF) here.
PUFs as Promising Tools for Security in Internet of Things
  Free Access Article (PDF) here.
High-Level Synthesis: Status, Trends, and Future Directions
  Free Access Article (PDF) here.
Accellera's DVCon Conferences Focus on the Community of Practicing Engineers
  Access Article (PDF) here.
2016 ASP-DAC
  Free Access Article (PDF) here.
Steven P. Levitan (1950-2016)
  Free Access Article (PDF) here.
And He Built a Crooked Chip
  Free Access Article (PDF) here.

 

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