For an embedded application, an ASIC approach provides a significant amount of performance gain, both in speed and energy, over a general-purpose processor approach in return for the loss of generality. On the other hand, a reconfigurable circuit such as an FPGA could achieve both of performance gain and generality with the proper design of the reconfigurable architecture. This talk covers two examples of such reconfigurable architectures in our recent and current projects. The first architecture enhances dependability, especially soft-error resilience, with built-in adaptive redundancy. Any part of the circuit can be configured with a different level of redundancy, and thereby a good trade-off between reliability and circuit scale can be achieved. The second architecture obtains high energy efficiency with the use of a "Via-switch" which performs as a programmable via. A Via-switch can be formed in BEOL without using FEOL devices. Programmable interconnects, which occupy considerable silicon area in a conventional FPGA, can be a simple crossbar placed on top of logic blocks. This overlay structure enables a highly area-efficient reconfigurable device called Via-switch FPGA with high energy efficiency. A Proof-of-Concept Via-swith FPGA has been designed and taped out for fabrication.
Hidetoshi Onodera received the B.E., and M.E., and Dr. Eng. degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983, and currently a Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability.
Dr. Onodera served as the Program Chair and General Chair of ICCAD and ASPDAC. He was the Chairman of IEEE Kansai Section, and the Vice President of Awards in IEEE CEDA Executive Committee.
He served as the Editor-in-Chief of IEICE Transactions on Electronics and IPSJ Transactions on System LSI Design methodology.
He is an IEEE Fellow, an IEICE Fellow, and a Member of Science Council of Japan.