As the technology scales, process, voltage and temperature, variations (PVT) and model inaccuracies impact design yield. In this talk predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. The methodology hinges on Mixture Important Sampling (MIS) is 5-6 orders of magnitude faster than Monte Carlo and few orders compared to recent techniques. For advanced technologies, we extend the methodology to enable key features such as Front End of the Line (FEOL) and back end of the line (BEOL) parasitic extraction and TCAD for manufacturability for 16nm and below. This increases the statistical confidence in the functionality and operability of the system-on-chip as a whole. We present design case studies both in planar and non- planar technologies.
Also Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability (BTI) effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning of life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.
Dr. Rajiv V. Joshi is a research staff member and key technical lead at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies from sub-0.5μm to 14nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. He has extensively worked on novel memory designs. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 60 invention plateaus and has over 235 US patents and over 354 including international patents. His interests are in in-memory computation, CNN, DNN accelerators and Quantum computing. He has authored and co-authored over 200 papers. He has given over 45 invited/keynote talks and given several Seminars. He is awarded prestigious IEEE Daniel Noble award for 2018. He received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He is a member of IBM Academy of technology and a master inventor. He served as a Distinguished Lecturer for IEEE CAS and EDS society. He is Distinguished visiting professor at IIT, Roorkie. He is IEEE, ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay. He served in the Board of Governors for IEEE CAS as industrial liaison. He serves as an Associate Editor of TVLSI. He will and has served on committees of DAC 2019, AICAS 2019, ISCAS, ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conference, ISQED and Advanced Metallization Program committees. He initiated IBM CAS EDS symposium at IBM in 2017 and will continue into 2018 with Artificial Intelligence as the focal area. He served as a general chair for IEEE ISLPED. He is an industry liaison for universities as a part of the Semiconductor Research Corporation. Also he is in the industry liaison committee for IEEE CAS society.