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Moore's Law is Dead, Long Live Moore's Law: Addressing the Power Efficiency, Reliability and Security Challenges of Technology Scaling

Moore's Law is Dead, Long Live Moore's Law: Addressing the Power Efficiency, Reliability and Security Challenges of Technology Scaling

Prof. Siddharth Garg,
University of Waterloo, Canada


April 8th, 2014, 10:00


Room H120 Technologiefabrik

For almost four decades, semiconductor technology scaling, as predicted by Moore's law, resulted in a win-win proposition in terms of the performance, power efficiency, functionality and cost of digital electronic devices.
Of late, however, several critical roadblocks have emerged that threaten the viability of the conventional technology scaling model: these include higher power density and on-chip temperature, reduced device reliability, and compromised security because of outsourced semiconductor design and manufacturing. To address these concerns, fundamentally new solutions at the circuit, architecture and system-level are required. I will present examples of two such solutions from my recent research.

In the first part of the talk, I will discuss new micro-architectural approaches to address the so-called "dark silicon" problem. This refers to the fact we will soon reach a point where the power consumption of all transistors on the chip, when turned on at the same time, will exceed the maximum chip power budget, thus forcing a fraction of the chip to remain "dark". I will show how, using a combination of new test-time, design-time and run-time mechanisms, the overabundance of (potentially dark) transistors on the chip can be exploited to provide significant performance improvements within tight power and thermal budgets.

In the second part of the talk, I will discuss my research on mitigating hardware Trojan insertion attacks by malicious entities in semiconductor foundries using split manufacturing. The idea is to split an integrated circuit (IC) into two (or more) components that are manufactured at separate foundries, thus obfuscating design intent. The components are then re-assembed in a secure facility using 3D stacking, a new, commercially available IC packaging technology. I will present a formal, computational notion of security for split manufacturing, and techniques to optimally partition an IC into two (or more) components so as to maximize security. I will show how split manufacturing successfully raises the bar on the attacker for inserting an effective malicious hardware Trojan.

I will conclude by highlighting several avenues for future research that will enable Moore's Law to deliver on it's promise of higher performance and more power efficient, reliable and secure computing devices in the technology generations to come.

Short Bio:
Siddharth Garg received a Ph.D. degree in Electrical and Computer Engineering (ECE) from Carnegie Mellon University (CMU), a Master's degree in Electrical Engineering from Stanford University and a Bachelor's degree also in Electrical Engineering from the Indian Institute of Technology (IIT) Madras. Since 2010, he has been a tenure-track Assistant Professor at the University of Waterloo in the Electrical and Computer Engineering Department. He is the recipient of several awards for his research contributions, including the Angel Jordan Award from CMU for outstanding thesis contributions, and best paper awards from the USENIX Security Symposium (2013), the SRC TECHCON (2010) and the International Symposium on Quality in Electronic Design (ISQED) in 2009.