Chair for Embedded Systems

Dr.-Ing. Marvin Damschen

  • Scientist

Short Bio

Marvin Damschen received his Ph.D (Dr.-Ing.) in Computer Science from the Karlsruhe Institute of Technology (KIT), Germany, under the supervision of Prof. Dr. Jörg Henkel in Dec. 2018. Currently, he is a postdoctoral researcher at the Chair for Embedded Systems at KIT. His main research interests are timing analysis and architectures for heterogeneous real-time systems with special focus on runtime-reconfigurable architectures.
Marvin Damschen received a B.Sc. degree - with distinction - and M.Sc. degree - with distinction - in Computer Science with a minor in Mathematics from the University of Paderborn, Germany, in 2012 and 2014, respectively.



Books / Book Chapters
Marvin Damschen, Martin Rapp, Lars Bauer, Jörg Henkel
i-Core: A runtime-reconfigurable processor platform for cyber-physical systems
Chapter in Embedded, Cyber-Physical, and IoT Systems: Smart Cameras, Hardware/Software Co-Design, and Multimedia — Essays Dedicated to Marilyn Wolf on the Occasion of Her 60th Birthday
to appear. Springer International Publishing, 2019


Marvin Damschen, Frank Mueller, Jörg Henkel
Co-Scheduling on Fused CPU-GPU Architectures with Shared Last Level Caches
in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),ESWEEK Special Issue, 2018 (accepted)
Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio Buttazzo, and Jörg Henkel
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing with FPGAs
in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2018 (accepted)
Marvin Damschen, Lars Bauer, Jörg Henkel
CoRQ: Enabling Runtime Reconfiguration under WCET Guarantees for Real-Time Systems
in IEEE Embedded Systems Letters (ESL), (accepted).
Marvin Damschen, Lars Bauer, Jörg Henkel
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors
in ACM Transactions on Architecture and Code Optimization (TACO), Vol.13, Issue 4, Article No.45, DOI , PDF, Dec. 2016.
Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
Invasive Computing for Timing-Predictable Stream Processing on MPSoCs
in it – Information Technology (IT), Band 58, Heft 6, DOI, PDF, Dez. 2016.
Marvin Damschen, Lars Bauer, Jörg Henkel
Timing Analysis of Tasks on Runtime Reconfigurable Processors
in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.25, Issue 1, pp. 294-307, DOI, PDF, Jan. 2017.


Marvin Damschen, Lars Bauer, Jörg Henkel
WCET Guarantees for Opportunistic Runtime Reconfiguration
in IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD), Westminster, CO, (accepted), November 4-7, 2019
Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker
Auto-SI: An Adaptive Reconfigurable Processor with Run-time Loop Detection and Acceleration
in 30th IEEE International System-on-Chip Conference (SOCC)
Munich, Germany, September 5-8, 2017.
Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare, Jörg Henkel
Floating Point Acceleration for Stream Processing Applications in Dynamically Reconfigurable Processors
in IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia’15)
Amsterdam, The Netherlands, October 8-9, 2015.
M. Damschen, H. Riebler, G. Vaz, and C. Plessl
Transparent offloading of computational hotspots from binary code to Xeon Phi
in IEEE/ACM 18th Design, Automation and Test in Europe Conference (DATE'15)
EDA Consortium, Grenoble, France, Pages 1078–1083, March 9-13, 2015.


Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat, Michael Bader
Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model using Reconfigurable Hardware in Invasive Computing
in 10th Workshop on UnConventional High Performance Computing (UCHPC)
Santiago de Compostela, Spain, August 28/29, 2017.
M. Damschen and C. Plessl
Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
in The 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT'15)
Amsterdam, The Netherlands, January 21, 2015.


Invited Talks
Timing Analysis for Runtime-Reconfigurable Architectures / Predictability Consideration for Fused CPU-GPU Architectures
Georgia Institute of Technology, Atlanta, GA, USA, October 16, 2017
Timing Analysis for Runtime-Reconfigurable Architectures
CSC801: Seminar in Computer Science (System Group)
North Carolina State University, Raleigh, NC, USA, August 25, 2017
Timing Analysis for Reconfigurable Architectures
3rd GI/ITG Workshop on Reconfigurable Systems: Architectures, Tools,Applications
Darmstadt, Germany, April 10/11, 2017


Marvin Damschen, Lars Bauer, Jörg Henkel
Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures
Ph.D. Forum at IEEE/ACM 22nd Design, Automation and Test in Europe Conference (DATE'19), Florence, Italy, March 25 - 29, 2019.



  • Doctoral Thesis:
    Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures PDF
  • Master Thesis:
    Easy-to-use on-the-fly binary program acceleration on many-cores PDF
  • Bachelor Thesis:
    Concurrent shared memory access for Android applications and real-time processes PDF


Student Theses