Research Areas

The Chair for Embedded Systems is devoted to Research in Design and Architectures for Embedded Systems.
A current focus of research are multi-core systems, dependability and low power design.
The Chair has currently the following research groups:

Resource-Constrained Machine Learning

The number of devices that autonomously interact with the real worls is growing fast, not least because of the rapid growth of the internet of things. Low manufacturing costs and low power/energy consumption are key for manufacturing such devices in large quantities. As a consequence, the devices have very limited resources w.r.t. computational power, energy, storage, or communication.

Simultaneously, there is a strong trend towards employing machine learning-based algorithms on end-devices to process input data such as images, videos, or sensor data in general. This not only comprises on-device inference but more importantly also on-device online learning. Online on-device learning enables us to build adaptable and customizable devices that can be employed in dynamically-changing environments.

In our chair, we focus on how to enable continuous on-device online learning. This problem can only be solved by considering all levels. Algorithm-level techniques that for instance leverage changes in the topologies and learning parameters of neural networks are equally relevant as software-level techniques that enable resource-aware learning, and hardware-level techniques like accelerators for efficient usage of available resources. Finally, we study distributed systems in which many independent resource-constrained devices cooperatively learn.

Martin Rapp
Kilian Pfeiffer

Low Power and Thermal-Aware Design


Advances in technology scaling in the nano-CMOS era have steadily increased the consumed power per chip area (i.e. power density). High power densities are the major reason for elevated on-chip temperatures. The trend of technology scaling, with supply voltage scaling reaching its limits, leads to discontinuation of Dennard Scaling. It may be feasible to only power on a subset of cores at full performance during the same time window. This causes the so-called dark silicon  problem [1]: it mandates that even though a chip may have a plenty of computation and communication resources, it is inevitable to keep some powered off or not running at full performance in order to fulfill chip’s thermal constraints like TDP (Thermal Design Power).

Recent research has shown though that the commonly used TDP is too conservative. A new power budget concept, called Thermal Safe Power (TSP), is presented in [2]. TSP is an abstraction that provides safe power constraint values as a function of the number of simultaneously operating cores. To optimize for performance under temperature constraint while considering dark silicon, recent research [3,4] have introduced novel resource management techniques that exploit the system-level knowledge, e.g., application characteristics, to tackle the target optimization problem. More advanced research has started to employ machine learning [5] to cope with unknown applications and runtime variation.

Keeping chip temperatures within safe limits is required to also maintain reliability. This is since elevated temperatures negatively influence the lifetime akin to the acceleration of aging mechanisms such as Negative/Positive Bias Temperature Instability (N/PBTI), Hot Carrier Induced Degradation (HCID), Time-Dependent-Dielectric Breakdown (TDDB) etc. State-of-the-art industrial measurements have demonstrated that aging mechanisms simultaneously occur. Thus, recent research has investigated the interdependencies of them and established that looking individually at aging mechanisms results in underestimating their ultimate overall effect [6,7]. 

In summary, high power densities and thus elevated temperatures seriously jeopardize the chip’s reliability. Therefore, there is an essential need to develop novel techniques to mitigate the related problems. This is the key focus of this research area at CES.


[1] Jörg Henkel, Heba Khdr, Santiago Pagani, Muhammad Shafique, “New Trends in Dark Silicon”, (special session) in ACM/EDAC/IEEE 52nd Design Automation Conference (DAC), San Francisco, CA, USA,, DOI, PDF, Jun 7-11 2015. 
[2] Santiago Pagani, Heba Khdr, Waqaas Munawar, Jian-Jia Chen, Muhammad Shafique, Minming Li, Jörg Henkel, "TSP: Thermal Safe Power - Efficient power budgeting for many-core systems in dark silicon", International Conference on Hardware - Software Codesign and System Synthesis (CODES+ISSS), New Delhi, India, pp. 1-10, 2014.
[3] Heba Khdr, Santiago Pagani, Muhammad Shafique, Jörg Henkel, “Thermal Constrained Resource Management for Mixed ILP-TLP Workloads in Dark Silicon Chips”, in ACM/EDAC/IEEE 52nd Design Automation Conference (DAC), San Francisco, CA, USA, Jun 7-11 2015. 
[4] Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel, “Power density-aware resource management for heterogeneous tiled multicores”, in IEEE Transactions on Computers (TC), Vol.66, Issue 3, Mar 2017. 
[5] Martin Rapp, Anuj Pathania, Tulika Mitra, and Jörg Henkel, “Neural Network-based Performance Prediction for Task Migration on S-NUCA Many-Cores”, in IEEE Transactions on Computers (TC), 2020.
[6] Victor M. van Santen, Hussam Amrouch, Jörg Henkel, “Modeling and Evaluating the Gate Length Dependence of BTI”, in IEEE Trans. on Circuits and Systems (Vol 66, Issue 9), Sep 2019.
[7] Hussam Amrouch, Javier Martin-Martinez, Victor van Santen, Miquel Moras, Rosana Rodriguez, Montserrat Nafria, Jörg Henkel, "Connecting the Physical and Application Level Towards Grasping Aging Effects", IEEE 53rd International Reliability Physics Symposium (IRPS'15), Monterey, CA, USA, April 2015.

Dr. Heba Khdr
M.Sc. Martin Rapp
Prof. Dr. Jörg Henkel


Internet of Things

Recent technology advancements and emerging techniques in embedded systems, wireless communication, and sensors have enabled the design of small-size, ultra-low power, and low cost embedded devices which use the Internet as an infrastructure for connecting to each other to communicate, coordinate, compute and cooperate. This novel paradigm is Internet of Things (IoT). IoT is covering a wide range of applications including automotive, smart buildings and, of particular interest, healthcare monitoring [1].

The limited resources on the IoT devices and smart gateways call for novel and application-specific techniques for on-board processing, resource management, offloading schemes, etc [2]. From the embedded perspective, resource-awareness both in hardware platform and software application is necessary in the whole design process and at all abstraction layers. Designing efficient platforms and developing design tools, flows, and methodologies for these devices are some emerging area of research.

In summary, the new paradigm of IoT and particularly, healthcare monitoring systems have brought new challenges and new problems into the embedded design research field. Therefore, new solutions and novel techniques are needed to address these new issues. This is our key focus in this research group at CES.

Contact information:
Farzad Samie (Web, Email), Lars Bauer (Web, Email).

[1] Farzad Samie, Lars Bauer, Jörg Henkel, “IoT Technologies for Embedded Computing: A Survey”, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IoT day, Pittsburgh, PA, USA, October 2-7, 2016. PDF
[2] Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris, Joerg Henkel, “Distributed QoS Management for Internet of Things under Resource Constraints”, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IoT day, Pittsburgh, PA, USA, October 2-7, 2016. PDF


Security for Cyber-physical Systems

There have been repeated documented cyber attacks on control processes in cyber-physical systems (CPSs) and this trend is on the rise. Attackers could inject unwanted/malicious software that run in the background in the embedded control system. Such software could leak data, corrupt processes, provide access to unauthorized users and lead to catastrophic problems. In fact, Cyber Security is the biggest concern nowadays for researchers, industries as well as governments.
In our project, we are the first who demonstrate thermal side channel attacks using infrared images of processor chips. To achieve that, a unique setup, wherein the processor chip is cooled from underneath, has been built to obtain accurate, high-resolution thermal heat images of the die of a multi-core processor. Our project aims at providing the industry of processor chip design with new methodology on how attacks can be captured based on the run-time thermal behavior of processors. We collaborate in our project with researchers at the New York University who conduct research in cyber-physical systems.

In addition, we also investigate from the physical level all the way to the system level how reliability degradations due to e.g., aging mechanisms can open the door for emerging hardware security threats and attacks in the current and upcoming technology nodes.
This is because technology scaling is approaching its limit in which displacing a few atoms within transistors due to aging phenomena may permanently or temporally endanger the functionality of the entire on-chip system leading to new kinds to security attacks. Such attacks are, unlike the traditional security attacks that have been intensively studied in the last few decades, cannot be traced back because the underlying mechanisms can naturally heal and recover after the attack ends. Therefore, such emerging security attacks due to degradation effects are significantly more challenging and research is still in its infancy.

Recorded infrared video, captured by our built thermnal setup, of an 8-core processor while running periodical task migration on top of Linux OS is available here

Research Group Leader: Dr.-Ing. Hussam Amrouch
Head of CES: Prof. Jörg Henkel

[1] Hussam Amrouch, Prashanth Krishnamurthy, Naman Patel, Jörg Henkel, Ramesh Karri, Farshad Khorrami, "Emerging (Un-)Reliability Based Security Threats and Mitigations for Embedded Systems" in IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'17), OCTOBER 15-20, Seoul, South Korea, 2017, PDF.
[2] Hussam Amrouch, Jörg Henkel, "Lucid Infrared Thermography of Thermally-Constrained Processors" in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'15), Rome, Italy, July 22-24, 2015, PDF.
[3] Interview in the KITLOOK Magazine, PDF



Dependable Hardware

As technology scaling reaches its limit, where displacing a few atoms within a transistor may endanger its entire functionality, the big picture behind aging, degradations, and reliability becomes more complex than often assumed. In our research group, we are the first who explore the instantaneous effects of aging which is a recent discovery that bears a large potential for reliability optimization. Though aging in general is known for a long time and the physical causes behind it such as bias temperature instability (BTI) have been extensively studied in last decade, investigating the impact of instantaneous aging on circuits’ reliability is still in its infancy. Traditionally, aging is treated as a long-term degradation of reliability in which it gradually degrades the chip’s performance over months or years. However, it has been recently reported that the effects of BTI may also be observed in a significantly shorter time domain, i.e. in the order of milliseconds or even microseconds [1, 2].

In our research group, we study different degradations effects (BTI, HCI, RTN, RDF, PV, etc.) from the physical level all the way up to the system level towards providing designers at the systems level with abstracted, yet sufficiently accurate reliability estimations [3, 4]. To achieve that, we collaborate with different international research groups with varied expertise.

Our developed models, software tools and degradation-aware cell libraries are made publicly available allowing other researchers to directly employing them without requiring any further modifications. For more information please visit our research page.

Contact information:
Research Group Leader: Dr.-Ing. Hussam Amrouch

[1] Victor M. van Santen, Hussam Amrouch, Javier Martin-Martinez, Montserrat Nafria, Jörg Henkel “Designing Guardbands for Instantaneous Aging Effects” in ACM/EDAC/IEEE 53rd Design Automation Conference (DAC’16), Austin, TX, USA, June 5-9, 2016 (accepted).
[2] Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel, “Aging-Aware Voltage Scaling” in IEEE/ACM 19th Design, Automation and Test in Europe Conference (DATE’16), Dresden, Germany, pp. 576-581, 2016.
[3] Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel “Reliability-Aware Design to Suppress Aging” in ACM/EDAC/IEEE 53rd Design Automation Conference (DAC’16), Austin, TX, USA, June 5-9, 2016 (accepted).
[4] Hussam Amrouch, Javier Martin-Martinez, Victor van Santen, Miquel Moras, Rosana Rodriguez, Montserrat Nafria and Jörg Henkel, “Connecting the Physical and Application Level Towards Grasping Aging Effects”, in IEEE 53rd International Reliability Physics Symposium (IRPS’15), CA, USA, pp. 3D.1.1-3D.1.8, 2015.


Adaptive and Self-Organizing On-Chip Systems

Embedded systems are no longer designed and dedicated to a specific and narrow use case. Instead, they are often expected to provide a large degree of flexibility, for instance, users of handhelds can download and start new applications on demand. These requirements can be addressed at different levels for embedded multi-/many core systems, i.e. the processor level and the system level. The main goal of this group is to investigate adaptivity at these levels in order to:

  • increase the performance to fulfill the user's expectations or constraints
  • increase the efficiency, e.g. ‘performance per area' or ‘performance per energy'
  • increase the reliability, i.e. the correct functionality of the system needs to be tested regularly and if
    a component is faulty it needs to be repaired (e.g. by using redundancy) or avoided (i.e. not used any more)

Adaptive-on-chip systemAt the processor level, this group investigates processor microarchitectures (e.g. caches and execution control) and different types of reconfigurable processors (allow changing parts of their hardware at run time). Reconfigurable processors can be realized by hardware structures that are used in FPGAs (field-programmable gate arrays) as they allow changing parts of the FPGA configuration at run time. These run-time reconfigurable processors are often used to provide application-specific accelerators on demand. A run-time system is used to decide which accelerators shall be reconfigured, which is especially challenging in multi-tasking and multi-core scenarios. Run-time reconfiguration can also be used to improve the reliability of a system, which is important in environments with a high radiation (space missions) and for devices that are built using unreliable manufacturing processes (as observed and predicted for upcoming nanometer technology nodes). Here, run-time reconfiguration can help to test the functionality of the underlying hardware, to correct temporary faults, and to adapt to permanents faults. In addition to microarchitectures and run-time systems, also compiler support for reconfigurable processors is investigated to enable a programmer-friendly access to the concepts of reconfigurable processors.

For multi-/many core systems as e.g. Intel's Single-chip Cloud Computer (SCC, providing 48 Pentium-like cores on one chip) or even larger systems, the question arises how these systems can be managed in an efficient way. For instance, the decisions ‘which application obtains how many cores' and ‘on which cores it shall execute' are crucial for performance and efficiency. A run-time system is required that scales with the number of cores and the number of applications that shall execute. Among others, it needs to consider the communication between the applications, the available memory bandwidth, or the temperature of the cores. Strategies that are based on distributed components that negotiate with each other (so-called Agents) are investigated for maintaining scalability and flexibility.

[1] Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel, "RISPP: rotating instruction set processing platform", ACM/IEEE/EDA 44th. Design Automation Conference (DAC'07), San Diego, CA, USA, pp. 791-796. June 2007.
[2] Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel, "Run-time adaptive on-chip communication scheme", IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), San Jose, California, USA, pp. 26-31, Nov. 2007.
[3] Muhammad Shafique, Lars Bauer, Jörg Henkel, "Adaptive Energy Management for Dynamically Reconfigurable Processors", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, Issue 1, pp. 50-63, Jan. 2014.



Check also: CES PhD Thesis