IEEE Design&Test Vol. 38, Issue 4

  • Speaker:
    Special Issue on Machine Intelligence at the Edge
  • Location:

    IEEE Explorer

  • Date: July/August
Design & Test

Magazine
Volume 38, Issue 4 (July/August)

Highlights
Special Issue on "Machine Intelligence at the Edge"
Special Issue on "SBCCI 2019"
General Interst Paper by Arunmozhi Manimuthu and Venugopal Dharshini  "Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance"
General Interest Paper by Samuel Pagliarini, Joseph Sweeney, Ken Mai, Shawn Blanton, Larry Pileggi, and Subhasish Mitra "Split-Chip Design to Prevent IP Reverse Engineering"
General Interst Paper by Yi-Hsin Wu, Jui-Yu Huang, Yi-Chun Yao, Yin-Jing Tien, Cheng-Juei Yu, and Sheng-De Wang "Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes"

July/August 2021 Content


From the EIC
Machine Intelligence at the Edge
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Special Issue on Machine Intelligence at the Edge
Guest Editors’ Introduction: Machine Intelligence at the Edge
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Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign
  This work is an introduction and a survey for the Special Issue on Machine Intelligence at the Edge. The authors argue that workloads that were formerly performed in the cloud are increasingly moving to resource-limited edge computing systems, which raises a new set of challenges for machine learning as well as new opportunities. read more
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Toward Energy–Quality Scaling in Deep Neural Networks
  This article surveys the latest advances in neural network (NN) architectures by applying them to the task of energy-quality scaling. Results show that, while coarse scaling is possible with existing NN architectures, fine-grain scaling is needed for fog computing efforts, and further work should focus on hybrid NN architecture development. read more.
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EdgeAl: A Vision for Deep Learning in the IoT Era
  This article discusses current directions in computation-aware deep learning and describes two new challenges in the IoT era: 1) data-independent deployment of learning and 2) communication-aware distributed inference. It presents new directions to alleviate these challenges. read more.
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Multisensing System for Parkinson’s Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier
  This article presents an FPGA-based system with combined electroencephalographic (EEG) and electromyography (EMG) to diagnose the stage of Parkinson’s disease. read more.
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A Mixture of Experts Approach for Low-Cost DNN Customization
  This article introduces a novel architecture for local learning, namely mixture of experts (MoEs), to customize a deep neural network (DNN) that is deployed on an edge device with performance improvement and low implementation overhead. read more
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Special Issue on SBCCI 2019
Guest Editors’ Introduction: SBCCI 2019
  View full article (PDF).
Hardware Accelerator for Runtime Temperature Estimation in Many-Cores
  This article proposes a solution, based on a suitable HW accelerator, to allow temperature estimation in complex many-core devices. read more.
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Security Vulnerabilities and Countermeasures in MPSoCs
  This article deals with software attacks targeting multiprocessor systems-on-chip and proposes a set of countermeasures corresponding to lightweight mechanisms characterized by a small impact on the system performance and area, while still guaranteeing a good level of protection. read more.
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Adaptive Integer Linear Programming Model for Optimal Qubit Permutation
  Quantum computer performance is often limited by the maximum number of pairs of qubits that can interact. This article expresses the problem in terms of integer linear programming, showing that in this way we can identify an optimal solution. read more.
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Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.0
  This article describes the NMLSim 2.0 CAD and simulation tool, representing a step forward to support the design of circuits based on the NanoMagnetic Logic technology, characterized by an ultralow energy consumption and a computing to memory integration. read more.
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Design and Test of Digital Logic DNA Systems
  This article describes DNAr-Logic, a software package that provides easy design and test of digital logic circuits in DNA computing without requiring in-depth knowledge of chemistry. read more.
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General Interest Papers
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance
  In home area networks, many appliances share a power distribution network and all are potentially the cause and victims of sudden current, voltage, and power spikes. read more
View full article (PDF).
Split-Chip Design to Prevent IP Reverse Engineering
  Split-chip design combines integrated circuits (ICs) from two or more disparate (trusted and untrusted) foundries to create an integrated system on a chip. read more
View full article (PDF).
Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes
  This article proposes a robust calculation method for the identification of anomalies in IC manufacturing test data while eliminating the need of large storage of raw measurements. read more
View full article (PDF).

Departments

Holding Conferences Online in Pandemic Times: The DATE Experience
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The Last Byte: Being Learned
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