Short Bio

Fazal Hameed received his M.S. in Electronics Engineering from Ghulam Khan Institute of Science and Technology, Pakistan in 2006. He is currently serving as a PhD student at the Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT), Germany. He is working in the Multi-core group with a focus on processor and cache architectures. His main research area is computer architecture with a special interest on SRAM and DRAM caches. He received CODES+ISSS'13 best paper nomination for his work on DRAM cache management in multi-core systems. He is currently an IEEE student member. Mr. Hameed has also served as an external reviewer for major conferences in embedded systems and computer architecture.
 

Publications

• Fazal Hameed, Lars Bauer and Jörg Henkel
  Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture
  in IEEE/ACM Design Automation Conference (DAC'14), San Francisco, CA, USA, (accepted).
   
• Fazal Hameed, Lars Bauer and Jörg Henkel
  Simultaneously Optimizing DRAM Cache Hit Latency and Miss Rate via Novel Set Mapping Policies
  in International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES'13), Montreal, Canada.
   
• Fazal Hameed, Lars Bauer and Jörg Henkel
  Reducing Inter-Core Cache Contention with an Adaptive Bank Mapping Policy in DRAM Caches
  in IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), Montreal, Canada.
  (Best Paper Nomination)
   
• Fazal Hameed, Lars Bauer and Jörg Henkel
  Adaptive Cache Management for a combined SRAM and DRAM cache hierarchy for Multi-cores
  in IEEE/ACM 16th Design Automation and Test in Europe Conference (DATE´13), Grenoble, France
   
• Fazal Hameed, Lars Bauer and Jörg Henkel
  Dynamic Cache Management in Multi-core Architectures through run-time adaptation
  in IEEE/ACM 15th Design Automation and Test in Europe Conference (DATE´12), Dresden, Germany
   
• Fazal Hameed, Mohammad Abdullah Al Faruque and Jörg Henkel
  Dynamic Thermal Management in 3D Multi-Core Architecture through Run-time Adaptation
  in IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE´11), Grenoble, France