The design of embedded processors, especially for IoT, personal mobiles, navigators, etc., has experienced significant progress since past few years. This development has been characterized by the increasing demand for application-specific solutions in order to fulfill the diverse and contradictory requirements of low power consumption, high performance, low cost and most importantly an efficient time-to-market deployment of those processors.
Application Specific Instruction Set Processors (ASIP) are customized processors, having a specific instruction set targeting a specific application to achieve an optimal solution for the above requirements. This customization can be addressed at different architectural levels by defining customized instructions, including/excluding predefined hardware blocks or setting processor ‘s parameters.
The focus of this lab is to get hands-on expertise of state-of-the-art ASIP Tool-Suite and practice optimized processor design for embedded applications. We will select an example application, profile them, design ASIP targeting power/area/speed efficiency, and then use our infrastructure to benchmark the designed ASIP to com pare cost & benefit in terms of performance, power, area, etc.
The ASIP design flow includes analyzing and profiling the targeted application, defining an ASIP accordingly, creating the special instruction, embedding required hardware blocks or configuring different architectural parameters. The synthesizable hardware description and complete compiler tool chain are generated automatically, and then the customized processor is implemented on an FPGA platform. This processor can be benchmarked for performance, area, and power constraints using QuestaSim/ModelSim and Xilinx Vivado tools.
For this lab, the lab manuals and all exercises are available in English language.
Available infrastructure for an ASIP design flow is based on: