Architecture & Software Level Approaches to High Performance and Low Power SoC Design
Dr. Sungjoo Yoo
Samsung Electronics, Seoul, Korea
Room -101, Building 50.34
- Date: March 10th, 2008, 11:30am
This talk addresses two areas of SoC design: high performance on-chip network and low power software. The effective memory bandwidth and latency of memory access often determines the performance of high-end multimedia SoC’s. There have been several approaches to achieve high memory performance, mostly by exploiting open row and/or bank interleaving as much as possible. In this talk, after reviewing existing solutions briefly, we explain a real problem that limits the full potential of existing solutions. Then, we present a novel method to resolve this problem.
Recently, 3D stacked memory starts to offer higher memory bandwidth with multiple memory ports. It will be required to fully exploit the increased memory bandwidth in order to implement more complex and high quality applications, e.g. higher quality 3D graphics, with 3D stacked memory. However, a simple extension of existing on-chip network to use multiple memory ports may not realize the goal due to its limitations such as network congestion caused by the lack of knowledge on the global information of communication, constraints of sequential memory access to avoid a deadlock problem that might occur in accessing multiple slaves with out-of-order service, etc. In this talk, we explain those problems and explain our solutions to them. Regarding the power consumption issue, software has been and will continue to be one of the most important design objects. DVFS (dynamic voltage and frequency scaling) is the most effective method in lowering power consumption. It sets operating frequency to the ratio of remaining workload to deadline. Most of existing methods use the worst case execution time (WCET) as the remaining workload. However, since it will be rare to encounter the worst case, such a pessimistic assumption may lose chance to achieve further reduction in energy consumption. In this talk, we will present two methods of DVFS that exploit the statistical runtime information rather than worst case execution time. The first method, which scales supply voltage (Vdd), gives a mathematical formulation to the DVFS problem based on the statistical runtime information. The other method, which is also based on statistical runtime information, tackles the problem of simultaneously scaling the voltage of supply (Vdd) and body bias (Vbb) to reduce both switching and leakage power consumption.