Thermal Aware Performance Optimization of Multi-Core Processors
Prof. Sarma Vrudhula
Arizona State University, USA
- Date: July 2nd, 2012, 10:00am
For multi-core processors with many tens or hundreds of cores, it will not be technically feasible or economically justifiable to design a package that can dissipate the maximum possible heat. Packages can only target the average power consumption. Furthermore, large variations in software workload and manufacturing processes will result in greater spatial and temporal variations in power density than with earlier processors. For these reasons, maximizing the efficiency of multi-core processors will require software techniques to dynamically control the speeds and voltages of the individual processors, as well as dynamically migrate threads among the processors. Such techniques are referred to as Dynamic Thermal Management (DTM).
In this talk we present a framework for optimal dynamic thermal management techniques for multi-core processors. We address several problems involved in computing on-line, the voltage and frequency schedule (dynamic voltage and frequency scaling or DVFS)) and task-to-core allocation that will minimize the maximum execution time (makespan) of a set of tasks, subject to thermal constraints. The formulation includes accounting for the leakage dependence on temperature (LDT), and the relation (non-linear) between processor speed, voltage and temperature. Variants of these problems that include optimizing the performance (throughput) with task deadlines, as well optimizing the energy efficiency (performance-per-watt).
The dynamic thermal management algorithms have been implemented in a new, easily configurable and fast architectural level thermal simulator called Magma. Its features include (1) fast steady-state analysis for early design space exploration to examine trade-offs in various design parameters such as the number of cores, package thermal properties, etc., (2) algorithms for both on-line and off-line dynamic thermal management to maximize performance subject to thermal constraints.
The scheme for optimizing the energy efficiency has been implemented on quad-core Intel Sandy Bridge processor baord. MiBench benchmarks were executed under the proposed DVFS policy and compared with the existing ACPI policies available on Linux: “performance”, “powersave” and “ondemand”. A summary of the results will be presented comparing the existing policies with the closed-loop solution.
Sarma Vrudhula is a Professor in the School of Computing, Informatics and Decisions Systems Engineering at Arizona State University, and the Director of the NSF I/UCRC Center for Embedded Systems. He received the Bachelor of Mathematics from the University of Waterloo, Ontario, Canada, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California.
Dr. Vrudhula’s research work is in VLSI design automation and CAD with a focus on improving the power consumption and energy efficiency of digital systems. His research has covered new circuit architectures for low power, logic synthesis and optimization, system level dynamic power and thermal management of multicore processors, energy optimization of battery powered computing systems and wireless sensor networks, models and methods for the analysis and optimization of power and performance in the presence of process variations.