Building Reliable Systems From Unreliable Components

  • Speaker:
    Prof. Siddharth Garg

    University of Waterloo, Canada

  • Location:

    H 120,

  • Date: March 26th, 2013, 10:00am

In this talk, I will present some recent research results on low hardware overhead techniques for permananent fault detection and fault recovery. The proposed techniques utilize a redundant URISC co-processor: an ultra reduced instruction set processor that executes only one Turing complete instruction. The URISC can be used to emulate any instruction in the ISA of the main, potentially faulty, processor, thus enabling full fault coverage. I will present a number of optimizations that allow us to use the URISC processor for fault detection and fault recovery with low performance penalty and low fault detection latency. 

Short Bio:
Siddharth is currently an Assistant Professor of Electrical and Computer Engineering at the University of Waterloo in Canada. He received a Ph.D. degree in ECE from Carnegie Mellon University, an MS degree in EE from Stanford University and a B.Tech. degree in EE from IIT Madras. He was a recipient of the Angel Jordan Award for outstanding thesis contributions from CMU and best paper awards at ISQED 2009 and SRC Techcon 2010.