Abstract
Due to the massive presence of arithmetic operations in many compute-intensive tasks, the proposing of approximating in arithmetic operators is a key approach to drive energy efficiency in error-tolerant digital CMOS design. On the other hand, one of the methods of power dissipation reduction extensively used over the years is data encoding for the switching activity reduction. We present the data coding process for obtaining power-efficient arithmetic modules that operate directly with these codes. Firstly, we show, as a case study, the use of approximate adders in the Sum of Absolute Difference (SAD) metric of H.265/HEVC video compression and the trade-off between power and quality-compression. After, we present the concepts and examples of hybrid arithmetic operators and a step to approximate it. The techniques for low-power and approximate arithmetic operators will allow higher timing margins in the design, to accommodate aging effects and adverse operating conditions (Vdd and temperature variations), thus making the digital system, in particular, H.265/HEVC video compression operation more dependable.

Bio
Eduardo Antonio César da Costa received the five-year engineering degree in Electrical Engineering from the University of Pernambuco, Recife, Brazil, in 1988, the M.Sc. degree in electrical engineering from the Federal University of Paraiba, Campina Grande, Paraíba, Brazil, in 1991, and the Ph.D. degree in computer science from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2002. Part of his doctoral work was developed at the Instituto de Engenharia de Sistemas e Computadores (INESC-ID), Lisbon, Portugal. He is currently a Full Professor at the Catholic University of Pelotas (UCPel), Pelotas, Brazil. He is co-founder and coordinator of the Graduate Program on Electronic Engineering and Computing at UCPel. His research interests are VLSI architectures and low-power design.

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