TALK: A NBTI Reliability Framework from Atoms to Processors
Prof. Souvik Mahapatra
Dept of Electrical Engineering, IIT Bombay, India
- Date: Sept 10th, 2019, 11:00am
Negative Bias Temperature Instability (NBTI) continues to remain as a serious reliability concern in HKMG FinFETs and impacts the long term performance of CMOS circuits. It is therefore important to develop a modeling framework to estimate the NBTI limited end of life degradation in devices and the corresponding degradation in circuits for various mission profiles. Such a framework can be added to the existing Design Technology Co-Optimization (DTCO) flows for concurrent optimization of performance, power, area and aging (PPAA) of advanced CMOS chips. In this presentation a NBTI reliability framework will be described that can estimate the impact of gate stack processes (atoms) and MOSFET architectures on circuit reliability. A BTI analysis tool will be presented that can analyse experimental data across various technologies and processes. TCAD implementation of the framework will be shown to study FinFET scaling and impact of Gate All Around (GAA) NSFET architectures having different channel materials, and check quantum confinement and strain effects on NBTI. A compact model that can handle circuit degradation under arbitrary gate activity will be discussed, with some examples of circuit degradation under actual workload versus worst case DC cases. A simulation flow will be presented to link device and RO degradation to that of processors, which includes detailed characterization of standard cells under NBTI. Several benchmark circuits will be analyzed. Finally, the statistical aspect of device-level variability and variable reliability will be addressed, and connections will be made to estimate the variability associated with SRAM performance degradation.
Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-01 he was with Bell Labs, Lucent Technologies, Murray Hill, NJ, USA. Since 2002 he is with the Electrical Engineering department at IIT Bombay and presently a full professor. His research interests are CMOS scaling, reliability and memory devices. He has published over 150 papers in peer reviewed journals and conferences and delivered invited talks in major international conferences including IEEE IEDM and IRPS. He is a fellow of IEEE (Institute of Electrical and Electronics Engineers), INAE (Indian National Academy of Engineering) and IASc (Indian Academy of Sciences), and a distinguished lecturer of IEEE Electron Devices Society.