Highlights
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July/August 2020 Content
From the EIC
• | Special Issue on VTS |
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Special Issue on VTS
• | Selected Papers from IEEE VLSI Test Symposium |
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• | Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests |
Ensuring a tight correlation between pre-silicon static timing analysis (STA) and post-silicon timing analysis is essential to a robust design flow. Researchers from Intel describe a novel methodology to validate path level STA on silicon using standard scan architecture and path delay tests that are generated by commercial EDA tools. read more View full article (PDF). |
• | Scan Integrity Tests for EDT Compression |
Scan chains are the fundamental building blocks for DFT, and testing for scan integrity is the first step in a robust test methodology. This article describes scan integrity tests for embedded test compression structures. read more. View full article (PDF). |
• | Testing of Prebond Through Silicon Vias |
Testing of the interconnects in a 3-D stack is a complex and expensive process. The authors propose a method using prebond testing to reduce manufacturing cost and improve overall yield. read more. View full article (PDF). |
• | Determining Mechanical Stress Testing Parameters for FHE Designs with Low Computational Overhead |
Flexible hybrid electronics have complex mechanical stress failure mechanisms. Researchers from ASU propose a novel method to obtain the optimum set of mechanical stress patterns to cover all potential fault locations and exert the required mechanical stress as dictated by the application. read more View full article (PDF). |
• | Know Your Channel First, then Calibrate Your mmWave Phased Array |
This article proposes a new method for calibration of high-speed phased array antennas that includes all the system components and spans the full chain of communication. Online calibration is possible without pausing or interrupting the communication processing in any way. read more View full article (PDF). |
• | Hardware-Based Real-Time Workload Forensics |
Workload forensics is a key component of software security that collects and analyzes information to identify suspicious behavior. Researchers from UT Dallas explore a hardware alternative since it is immune from software attacks and does not rely on data collected from the OS or software applications. read more View full article (PDF). |
General Interest Papers
• | Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity |
GPGPU-Sim is widely used for simulating GPU performance. Hence, creating a parallel version of this tool is very useful to the broader research community. This article presents various characteristics of a parallel GPGPU-Sim simulator. read more View full article (PDF). |
• | Advances in Design and Test of Monolithic 3-D ICs |
Monolithic 3-D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic intertier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. read more View full article (PDF). |
• | Time-to-Digital Converter Compiler for On-Chip Instrumentation |
This article proposes an automatic compiler for an on-chip time-to-digital converter (TDC) that can be used for monitoring the on-chip operating conditions such as temperature and supply voltage. The proposed compiler adopts a resilient architecture and supports self-calibration and range adjustment. read more View full article (PDF). |
Tutorial Paper
• | A Survey of Silicon Photonics for Energy-Efficient Manycore Computing |
Silicon photonics is an emerging paradigm for designing energy-efficient and high-performance communication backbone for manycore chips. This article presents a survey about designing photonic on-chip infrastructure. read more View full article (PDF). |
Departments
• | The Last Byte: My Friendly Orange Glow |
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