Chair for Embedded Systems

IEEE Design&Test Vol. 38, Issue 1

  • Speaker:
    Special Issue on Hack@DAC
  • Location:

    IEEE Explorer

  • Date: January/February
Design & Test

Magazine
Volume 38, Issue 1 (January/February)

Highlights
Special Issue on "Competing to Secure SoCs"
Tutorial Paper by Brian Crafton, Samuel Spetalnick, Yan Fang, and Arijit Raychowdhury "Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads"
General Interest Paper by Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, and Christian Mayr "Real-time Hardware Implementation of ARM CoreSight Trace Decoder"

January/February 2021 Content


From the EIC
Special Issue Hack@DAC: Security Competition at the Design Automation Conference
  View full article (PDF).

Special Issue on Competing to Secure SoCs
Guest Editors’ Introduction: Education for Cyber-Physical Systems
  View full article (PDF).
SoC Security Evaluation: Reflections on Methodology and Tooling
  This article details a methodology to find bugs across multiple abstraction layers of the system, specifically at the hardware-software boundary. The article describes how existing tools can help with such methodology and limitations. read more
View full article (PDF).
Hardware Penetration Testing Knocks Your SoCs Off
  This article highlights how software simulations can, on the one hand, help uncover bugs, but on the other hand, help exploit them. read more.
View full article (PDF).
Hunting Security Bugs in SoC Designs: Lessons Learned
  This article presents a methodology for finding hardware security bugs, using Lint tools that use static analysis techniques, along with best practices for code reviews and developing test cases. read more.
View full article (PDF).
Texas A&M Hackin’ Aggies’ Security Verification Strategies for the 2019 Hack@DAC Competition
  This article details how well functional verification technique can catch security bugs in a resource-constrained setting. read more.
View full article (PDF).

Tutorial Papers
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads
  Designing hardware accelerators for machine learning (ML) applications is a well-researched problem. This article presents a tutorial regarding new computing architectures, circuits techniques, and multiple promising device technologies for in-memory computing targeting ML workloads. read more
View full article (PDF).
General Interest Papers
Real-time Hardware Implementation of ARM CoreSight Trace Decoder
  This article proposes a real-time ARM CoreSight trace decoder in hardware for system-on-chip design, analysis, and verification. read more
View full article (PDF).

Departments

Report on the 2020 Embedded Systems Week (ESWEEK): A Virtual Event during a Pandemic, September 20-25
  View full article (PDF).
The Last Byte: Hacking in the Dark
  View full article (PDF).