This package provides our integrated aging and error masking estimator along with example netlists of different circuits. Our integrated aging and error masking estimator performs gate-level analysis of a given netlist to quantify the error masking probabilities and aging of x% critical paths of a processor/hardware circuit. For that, the gate-level netlist describing the circuit is transformed into a graph and the paths are extracted. For the aging analysis, aging estimates of several basic logic elements are given as an input considering different device parameters, e.g., transistor dimensions, activity and temperature. Along with the signal probabilities from the ModelSim simulation, the aging can be estimated for x% critical paths, where the delay degradation can be observed over a period of 10 years. For the masking analysis, the masking properties of different gates are provided as an input. Afterwards, the types of gates on a path and the signal probabilities determining the masking potential are analyzed and are combined to the final masking potential of a complete path. This enables a detailed analysis of the behavior of a circuit under the impacts of soft errors and device aging. Further details can be found in our following DAC'14 paper.

Citation: In case of usage, please refer to our corresponding DAC 2014 publication:
Semeen Rehman, Florian Kriebel, Duo Sun, Muhammad Shafique, and Jörg Henkel, "dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects." 51th ACM/EDA/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 2014.