Dr.-Ing. Lokesh Siddhu
- Post-Doc
- room: B2-314.4
- phone: +49 721-608-46323
- lokesh siddhu ∂does-not-exist.kit edu
Haid-und-Neu-Str. 7
Bldg. 07.21
76131 Karlsruhe
Short Bio
Lokesh Siddhu received his B.Tech. degree in Electrical and Electronics Engg. from Guru Gobind Singh Indraprastha University, India, in 2009. He received a Master's degree (Aug 2009 - Jun 2011) from the Indian Institute of Science, India, in Electronics Design And Technology and then worked with Intel for 3.5 years (July 2011 - Dec 2014), looking into the design (timing, quality, noise, power) of various complex data-path blocks like multipliers, shifters, aligners.
He pursued his Ph.D. in Leakage Aware Dynamic Thermal Management for 3D Memory Architectures from Jan 2015 - June 2023 at the Department of Computer Science & Engg, Indian Institute of Technology, Delhi. He is currently a researcher at the Chair for Embedded Systems (CES) at the Karlsruhe Institute of Technology (KIT). His research interests include embedded systems, memory exploration, and optimization energy-efficient computing. He has received the best paper nomination at DATE 2022 for the work - "CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance."
Publications
| Journals | |
|---|---|
| Mohammed Bakr Sikal, Heba Khdr, Lokesh Siddhu, Jörg Henkel ML-Based Thermal and Cache Contention Alleviation on Clustered Manycores with 3-D HBM in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, Volume 43, Issue 11), DOI, PDF, Nov 2024. | |
| Lokesh Siddhu; Hassan Nassar; Lars Bauer; Christian Hakert; Nils Hölscher; Jian-Jia Chen; Jörg Henkel
Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs in IEEE Embedded Systems Letters (Volume 14, Issue 4), DOI, PDF, Dec 2023. | |
| Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory Systems in ACM Transactions on Architecture and Code Optimization (Volume 19, Issue 3), DOI, PDF, Apr 2022. https://github.com/marg-tools/CoMeT/ |
| Conferences | |
|---|---|
| Mina Ibrahim, Martel Shokry, Lokesh Siddhu, Lars Bauer, Hassan Nassar and
Jörg Henkel An FPGA-Based RISC-V Instruction Set Extension and Memory Controller for Multi-Level Cell NVM 2024 International Conference on Microelectronics (ICM), Doha, Qatar, DOI, PDF, Dec 14-17 2024. | |
| Jörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, and Ming-Liang Wei (Invited Paper) Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications in International Conference on Computer-Aided Design (ICCAD), Oct 27-31 2024. | |
| Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi Tahoori, Mahta Mayahinia, Jeronimo Castrillon, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications in International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), PDF, Sept 17-22 2023. |
| arXiv | |
|---|---|
| Yun-Chih Chen, Tristan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jeronimo Castrillon, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, Jürgen Teich Modeling and Simulating Emerging Memory Technologies: A Tutorial in arxiv, DOI, PDF, 2025. |
Student Theses
Abbreviation: B - Bachelor Thesis, M - Master Thesis
| Topic | Type of work | Mentor |
|---|---|---|
| Writing NVM Energy-Efficiently (PDF) | B / M | Siddhu, Lokesh / Bauer, Lars |
| Name | Type of work | Title | Mentor |
|---|---|---|---|
| Fuchs, Maximilian | Bachelor thesis | Reducing PCM Refresh Overheads for CNNs via Task Migration | Siddhu, Lokesh |
| Wedeck, Paul | Hiwi | Reducing PCM Refresh Overheads for CNNs via DVFS | Siddhu, Lokesh |
| Xu, Fengyuan | Bachelor thesis | Efficient Retention-Aware PCM Refreshing for Enhancing Neural Architecture Performance | Siddhu, Lokesh / Nassar, Hassan |
| Name | Type of work | Title | Mentor | Completion date |
|---|---|---|---|---|
| Ridinger, Nathan | Bachelor thesis | Improving Performance for NVM Memories using Fast Write Mode | Siddhu, Lokesh | 2024-09-24 |
| Götzfried, Erik | Bachelor thesis | Extending a RISC-V simulator to support fast writes for emerging non-volatile memories | Siddhu, Lokesh / Bauer, Lars | 2024-02-29 |
| Megalaa, Martel | Bachelor thesis | Adding Fast Write Instruction in RISC-V For Writing PCM Efficiently | Siddhu, Lokesh | 2023-08-30 |
| Shenouda, Mina | Bachelor thesis | Developing an FPGA-based Emulation Platform with a RISC-V architecture for Writing NVM Energy-Efficiently | Siddhu, Lokesh | 2023-08-20 |