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IEEE Design&Test Vol.34, Issue 1

  • Speaker:
    Special Issue on 3D-Test
  • Location:

    IEEE Explorer

  • Date: January/February
Design & Test

Magazine
Volume 34, Issue 1 (January/February)

Highlights
Special Issue on "3D-Test"  
Perspective by Mark Papermaster, "Developing Great Products for the Immersive Computing Era"
Tutorial by Andy D. Pimentel, "Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration"

January/February 2017 Content


From the EIC
• 3D Test
  View full article (PDF).

3D-Test
• Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory
  View full article (PDF).
• Unleashing Fury: A New Paradigm for 3-D Design and Test
  This paper, based on an excellent keynote address by AMD's Jeff Rearick at 3D-TEST 2015, describes ... read more.
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• High-Bandwidth Memory (HBM) Test Challenges and Solutions
  TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by ... read more.
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• High-Performance HBM Known-Good-Stack Testing
  Based on Loranger's talk at 3D-TEST 2015, this article details the dedicated developments performed at probe-card supplier ... read more.
View full article (PDF).

General Interest Papers
• Estimating the Impact of Methodology on Analog Integrated Circuit Design Time
  The article discusses analog design practices and proposes a project management model for studying ... read more.
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• Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias
  Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes ... read more.
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• A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications
  Testability is a perennial concern that requires ever-improved solutions; however, potentially resultant security vulnerabilities ... read more.
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• Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms
  Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents ... read more.
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Departments
• Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration
  View article (PDF).
• Developing Great Products for the Immersive Computing Era
  View article (PDF).
• An Interview With Semiconductor Pioneer and EDA Visionary Leader Wally Rhines
  Free Access Article (PDF).
• Report of the 2016 Embedded Systems Week (ESWEEK)
  Free Access Article (PDF).
• The 2016 DAC Art Show Grand Prize Winner: Coventor, Inc.
  Free Access Article (PDF).
• Research Is Its Own Reward
  Free Access Article (PDF).

 

Table-of-Contents