Abstract:
Against the background of nanotechnology, reliability concerns are arising with an alarming pace in current CMOS designs. The shrinking of technology sizes results in circuits that are susceptible to several errors sources like parameter variations, radiation or wear-out mechanism. In case of the latter, transistor and interconnection parameters degrade over time leading to possible errors and malfunctions. Related countermeasures include circuit hardening, redundancy techniques and graceful degradation approaches. The latter requires to system to be aware of its so-called Remaining Useful Lifetime (RUL), a parameter that results from the difference of the current lifetime of the system and it’s expected time to failure. This talk will give an overview about selected approaches for aging monitoring and lifetime extension developed at the “ASIC Reliability Group”. This includes solutions for intrusive and unintrusive monitoring, aging prediction based on learning during design time and a low power approach for lifetime extension.

Short Curriculum:
Frank Sill Torres received the Diploma and Dr.-Ing. degrees in Electrical Engineering from the University of Rostock, Germany, in 2002 and 2007, respectively. From 2007 to 2009 he was as Post-Doc at the Federal University of Minas Gerais (UFMG), Brazil, which was followed by a year in the industry. From 2010 to 2018, he was with the Department of Electronic Engineering at the UFMG as professor for microelectronics. In 2018, he joined the Cyber-Physical Systems group of the German Research Center for Artificial Intelligence (DFKI) in Bremen as Senior Researcher. His current research interests include Robust System Design, Low Power Design, and Emerging Technologies. Frank directs the “ASIC Reliability Group” at the UFMG, is an Associate Researcher of the Brazilian National research council, and member of several conference committees.